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AD7191

Rev. A | Page 16 of 20

TEMPERATURE SENSOR

Embedded in the AD7191 is a temperature sensor. The

temperature sensor is selected when the TEMP pin is tied

high. The TEMP pin has higher priority than the CHAN

pin; therefore, when TEMP is high, the temperature sensor

is selected irrespective of the polarity on the CHAN pin.

When the temperature sensor is selected, the device should

return a code of 0x800000 when the temperature is 0 K. A one-

point calibration is needed to get the optimum performance from

the sensor. Therefore, a conversion at 25°C should be recorded

and the sensitivity calculated. The sensitivity is 2815 codes/°C,

approximately. The equation for the temperature sensor is

Temp (K) = (Conversion− 0x800000)/2815 K

Temp (°C) = Temp (K) − 273

Following the one point calibration, the internal temperature

sensor has an accuracy of ±2°C, typically.

Each time the temperature sensor is selected, DOUT/RDY goes

high and remains high until the appropriate settling time

elapses. Therefore, any read operations should be completed

before selecting the temperature sensor. Otherwise, all 1s are

read back from the AD7191 as the DOUT/RDY pin is set high

following the channel change.

POWER-DOWN (PDOWN)

The PDOWN pin functions as a power-down pin and a reset

pin. When PDOWN is taken high, the AD7191 is powered

down and the DOUT/RDY pin is tristated. If the on-chip clock

is selected, it will be powered down also. If an external crystal is

being used, the on-chip oscillator circuitry remains active.

With PDOWN high, the circuitry and serial interface are also

reset. This resets the logic, the digital filter, and the analog

modulator. PDOWN must be held high for 100 ns minimum to

initiate the reset function.

When PDOWN is taken low, the AD7191 is taken out of power-

down mode. When the on-chip clock has powered up (1 ms,

typically), the modulator begins sampling the analog input, and

the DOUT/RDY pin becomes active. When an external crystal

or clock is used as the master clock source to the AD7191, the

1 ms power-up time is not required. A reset is automatically

performed on power-up.

CLOCK

The AD7191 has an internal 4.92 MHz clock that has a 4%

tolerance. The AD7191 can use the internal clock or, alterna-

tively, an external clock or crystal can be used. The CLKSEL

pin is used to select the clock source. When CLKSEL is low,

an external clock/crystal is selected. When CLKSEL is high,

the internal clock is selected. If a crystal is used, the crystal

should be connected between MCLK1 and MCLK2. The user

should refer to the crystal data sheet for details on the capacitor

values. If an external clock source is used, it should be applied

to MCLK1. MCLK2 should be left unconnected.

When the polarity of CLKSEL is changed, DOUT/RDY goes

high and remains high until the appropriate settling time elapses.

BIPOLAR CONFIGURATION

The AD7191 accepts a bipolar input range. A bipolar input

range does not imply that the part can tolerate negative voltages

with respect to system AGND. Signals on the positive analog

input pin are referenced to the voltage on the negative analog

input pin. For example, if AIN2 is 2.5 V, the analog input range

on the AIN1 input is 2.461 V to 2.539 V for a gain of 128 when

a 5 V reference is used.

DATA OUTPUT CODING

The AD7191 uses offset binary coding. Therefore, a negative

full-scale voltage results in a code of 000...000, a zero differen-

tial input voltage results in a code of 100...000, and a positive

full-scale input voltage results in a code of 111...111. The output

code for any analog input voltage can be represented as

Code = 2N – 1 × [(AIN × Gain/VREF) + 1]

where AIN is the analog input voltage (AIN1 – AIN2 or AIN3 –

AIN4), Gain is 1, 8, 64, or 128, and N = 24 for the AD7191.

BRIDGE POWER-DOWN SWITCH

The bridge power-down switch (BPDSW) is useful in battery-

powered applications where it is essential that the power

consumption of the system be optimized. A 350 Ω load cell

consumes 15 mA typically when excited with a 5 V power

supply. To minimize the current consumption, the load cell is

disconnected when it is not being used. The bridge power-

down switch can be included in series with the load cell. When

PDOWN is low, the bridge power-down switch is closed, and

the load cell measures the strain. When PDOWN is high, the

bridge power-down switch is opened so that no current flows

through the load cell. Therefore, the current consumption of

the system is minimized. The bridge power-down switch has an

on-resistance of 10 Ω maximum, and it is capable of

withstanding 30 mA of continuous current.

REFERENCE

The AD7191 has a fully differential input capability. The

common-mode range for these differential inputs is AGND to

AVDD. The reference input is unbuffered; therefore, excessive

R-C source impedances introduce gain errors. The reference

voltage REFIN (REFIN(+) − REFIN(−)) is AVDD nominal, but

the AD7191 is functional with reference voltages of 1 V to AVDD.

In applications where the excitation (voltage or current) of the

transducer connected to the analog input also drives the refer-

ence voltage for the part, the effect of the low frequency noise in

the excitation source is removed because the application is ratio-

metric. If the AD7191 is used in a nonratiometric application,

a low noise reference should be used.

Recommended 2.5 V reference voltage sources for the AD7191

include the ADR421, which is a low noise reference. These

references have low output impedances and are, therefore,

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