AD7764

Data Sheet

Rev. B | Page 6 of 33

TIMING SPECIFICATIONS

Table 3.

Parameter

Unit

Description

Min

Typ

Max

500

kHz

Applied master clock frequency

40

MHz

250

kHz

Internal modulator clock derived from MCLK

20

MHz

sec

SCO high period

sec

SCO low period

1

2.5

ns

SCO rising edge to FSO falling edge

2

3.5

ns

Data access time, FSO falling edge to data active

8

ns

MSB data access time, SDO active to SDO valid

40

ns

Data hold time (SDO valid to SCO rising edge)

9.5

ns

Data access time (SCO rising edge to SDO valid)

2

2.5

ns

SCO rising edge to FSO rising edge

sec

FSO low period

12

ns

Setup time from FSI falling edge to SCO falling edge

sec

FSI low period

sec

FSI low period

12

ns

SDI setup time for the first data bit

12

ns

SDI setup time

0

ns

SDI hold time

sec

Minimum time for a valid RESET pulse

5

ns

Minimum time between the MCLK rising edge and RESET rising edge

5

ns

Minimum time between the RESET rising edge and MCLK rising edge

sec

Minimum time for a valid SYNC pulse

5

ns

Minimum time between the MCLK falling edge and SYNC rising edge

5

ns

Minimum time between the SYNC rising edge and MCLK falling edge

1

This is the maximum time FSI can be held low when writing to an individual device (a device that is not daisy-chained).