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AD7764

Data Sheet

Rev. B | Page 16 of 33

THEORY OF OPERATION

The AD7764 features an on-chip fully differential amplifier to

feed the Σ-Δ modulator pins, an on-chip reference buffer, and a

FIR filter block to perform the required digital filtering of the

Σ-Δ modulator output. Using this Σ-Δ conversion technique

with the added digital filtering, the analog input is converted

to an equivalent digital word.

Σ-Δ MODULATION AND DIGITAL FILTERING

The input waveform applied to the modulator is sampled, and

an equivalent digital word is output to the digital filter at a rate

equal to fICLK. By employing oversampling, the quantization

noise is spread across a wide bandwidth from 0 to fICLK. This

means that the noise energy contained in the signal band of

interest is reduced (see Figure 30). To further reduce the

quantization noise, a high-order modulator is employed to

shape the noise spectrum so that most of the noise energy is

shifted out of the signal band (see Figure 31).

QUANTIZATION NOISE

fICLK/2

BAND OF INTEREST

Figure 30. Σ-Δ ADC, Quantization Noise

fICLK/2

NOISE SHAPING

BAND OF INTEREST

Figure 31. Σ-Δ ADC, Noise Shaping

fICLK/2

BAND OF INTEREST

DIGITAL FILTER CUTOFF FREQUENCY

Figure 32. Σ-Δ ADC, Digital Filter Cutoff Frequency

The modulator sampling rate, fICLK, is dependent on the power

mode chosen. Table 6 details the relationship between MCLK

and fICLK across power mode. The AD7764 low power mode

divides the MCLK by a factor of 4, reducing current consumption

in both the analog and digital domains.

Table 6. Modulator Sampling Rate vs. Power Mode

Power Mode

Modulator Sampling Rate (fICLK)

Normal

MCLK/2

Low

MCLK/4

The digital filtering that follows the modulator removes the

large out-of-band quantization noise (see Figure 32) while also

reducing the data rate from fICLK at the input of the filter to fICLK

/64 or less at the output of the filter, depending on the decimation

rate used.

–160

–140

–120

–100

–80

–60

–40

–20

300

250

200

150

100

FREQUENCY (kHz)

PASS-BAND RIPPLE = 0.05dB

–0.1dB FREQUENCY = 125.1kHz

–3dB FREQUENCY = 128kHz

STOP BAND = 156.25kHz

Figure 33. Filter Frequency Response (312.5 kHz ODR)

The AD7764 employs a sequence of three FIR filters in series to

provide a digital filter with a low ripple pass band, a steep

transition band, and excellent stop-band rejection, which starts

at the Nyquist frequency. Achieving the stop-band rejection at

the Nyquist frequency is beneficial because it prevents signals

slightly greater than the Nyquist frequency, which are not protected

by and external antialias filter from aliasing back in-band.

The AD7764 digital filter allows data to be output at three

different output data rates (for any given MCLK input frequency)

through setting the decimation ratio through the series of filters.

The first filter receives data from the modulator at fICLK MHz,

where it is decimated 4× to the output data at (fICLK/4) MHz.

The second filter allows the decimation rate to be chosen from

8× to 32×. The third filter has a fixed decimation rate of 2×.

Digital filters exhibit a group delay and settling time. The group

delay of the filter is the delay from the change in analog input to

when it is output by the digital filter. It is comprised of the comp-

utation plus the filter delays. The delay until valid data is available

(when the FILTER_SETTLE status bit is set) is approximately

twice the filter delay plus the computation delay.

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