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AD7764 Datasheet(PDF) 19 Page - Analog Devices |
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AD7764 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 34 page ![]() AD7764 Data Sheet Rev. B | Page 18 of 33 Table 8. Filter Group Delay and Settling Time in Normal Power Mode Decimation Rate Filter Computation Delay (tMCLK) Filter Delay (tMCLK) tGDMCLK ADC Group Delay (tMCLK) tSYNC_OFFSET (tMCLK) tSYNC_FS SYNC to FILTER_ SETTLE Bit (tMCLK) Modulator Sampling Rate (fICLK) Oversampling Ratio (OSR) Filter Pass Band Output Data Rate (ODR) 64× 80 3504 3584 87 7128 MCLK/2 64 ODR × 0.4 MCLK/64 128× 113 6960 7073 141 13,966 MCLK/2 128 ODR × 0.4 MCLK/128 256× 443 13,608 14,051 252 27,901 MCLK/2 256 ODR × 0.4 MCLK/256 Table 9. Filter Group Delay and Settling Time for Low Power Mode Decimation Rate Filter Computation Delay (tMCLK) Filter Delay (tMCLK) tGDMCLK ADC Group Delay (tMCLK) tSYNC_OFFSET (tMCLK) SYNC to FILTER_ SETTLE Bit (tMCLK) Modulator Sampling Rate (fICLK) Oversampling Ratio (OSR) Filter Pass Band Output Data Rate (ODR) 64× 120 3552 3672 113 7282 MCLK/4 32 ODR × 0.4 MCLK/64 128× 162 7008 7170 167 14,248 MCLK/4 64 ODR × 0.4 MCLK/128 256× 224 13,920 14,144 277 27,926 MCLK/4 128 ODR × 0.4 MCLK/256 |
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