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Data Sheet

AD7690

Rev. C | Page 19 of 24

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7690s are connected

to an SPI-compatible digital host.

A connection diagram example using two AD7690s is shown in

Figure 38, and the corresponding timing is given in Figure 39.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback. (If SDI and CNV are low, SDO is

driven low.) Prior to the minimum conversion time, SDI can be

used to select other SPI devices, such as analog multiplexers,

but SDI must be returned high before the minimum conversion

time elapses and then held high for the maximum possible

conversion time to avoid the generation of the busy signal

indicator. When the conversion is complete, the AD7690 enters

the acquisition phase and powers down. Each ADC result can

be read by bringing its SDI input low, which consequently

outputs the MSB onto SDO. The remaining data bits are clocked

by subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can be used to capture the data,

a digital host using the SCK falling edge allows a faster reading

rate, provided it has an acceptable hold time. After the 18th SCK

falling edge or when SDI goes high (whichever occurs first), SDO

returns to high impedance and another AD7690 can be read.

Figure 38. 4-Wire CS Mode Without Busy Indicator Connection Diagram

Figure 39. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing

DATA IN

CLK

CS1

CONVERT

CS2

DIGITAL HOST

CNV

SCK

SDO

SDI

CNV

SCK

SDO

SDI

AD7690

SDO

D17

D16

D15

tDIS

SCK

tHSDO

tDSDO

tEN

CONVERSION

ACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

SDI(CS1)

CNV

tSSDICNV

tHSDICNV

tSCK

tSCKL

tSCKH

D17

D16

SDI(CS2)

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