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AD7690 Datasheet(PDF) 21 Page - Analog Devices

Part # AD7690
Description  400 kSPS PulSAR Differential ADC in MSOP/LFCSP
PDF  25 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7690 Datasheet(HTML) 21 Page - Analog Devices

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AD7690
Data Sheet
Rev. C | Page 20 of 24
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7690 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This independence is particularly important in applications where
low jitter on CNV is desired.
The connection diagram is shown in Figure 40, and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7690
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 19th SCK falling edge or
SDI going high (whichever occurs first), SDO returns to high
impedance.
Figure 40. 4-Wire CS Mode with Busy Indicator Connection Diagram
Figure 41. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
DIGITAL HOST
47kΩ
CNV
SCK
SDO
SDI
AD7690
SDO
D17
D16
D1
D0
tDIS
SCK
12
3
17
18
19
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV



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