TSB41BA3IPFP datasheet(30/63 Pages) TI

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TSB41BA3

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS155A − MAY 2003 − REVISED OCTOBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

NOTE:

The total frequency variation must be kept below

±100 ppm from nominal with some allowance for

error introduced by board and device variations. Trade-offs between frequency tolerance and

stability may be made as long as the total frequency variation is less than

±100 ppm. For example,

the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance

may be specified at 30 ppm to give a total of 80 ppm possible variation due to the oscillator alone.

Aging also contributes to the frequency variation.

D Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent

upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function of not only the

discrete load capacitors, but also board layout and circuit. It may be necessary to iteratively select discrete

load capacitors until the PCLK output is within specification. It is recommended that load capacitors with

a maximum of

±5% tolerance be used.

As an example, for the OHCI + 41LV03 evaluation module (EVM) which uses a crystal specified for 12 pF

loading, load capacitors (C9 and C10 in Figure 10) of 16 pF each were appropriate for the layout of that particular

board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals

(CPHY), and the loading of the board itself (CBD). The value of CPHY is typically about 1 pF, and CBD is typically

0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and

C10 combine as capacitors in series so that the total load capacitance is:

L +

C10

) C10 )

PHY ) CBD

49.152 MHz

CPHY + CBD

C10

Figure 10. Load Capacitance for the TSB41BA3 PHY

NOTE: The layout of the crystal portion of the PHY circuit is important for obtaining the correct

frequency, minimizing noise introduced into the PHY’s phase lock loop, and minimizing any

emissions from the circuit. The crystal and two load capacitors must be considered as a unit during

layout. The crystal and load capacitors must be placed as close as possible to one another while

minimizing the loop area created by the combination of the three components. Varying the size of

the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant current

(IS) that flows in this resonant circuit. This layout unit (crystal and load capacitors) must then be

placed as close as possible to the PHY XI and XO terminals to minimize trace lengths.

C10

Figure 11. Recommended Crystal and Capacitor Layout

TSB41BA3IPFP Datasheet(PDF) 30 Page - Texas Instruments

TSB41BA3IPFP Datasheet(HTML) 30 Page - Texas Instruments

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