AL440B

AL440B

November 28, 2001

6

The internal structure of the AL440B consists of an Input/Output buffers, Write Data Registers, Read

Data Registers and main 512k x8 memory cell array and the state-of-the-art logic design that takes

care of addressing and controlling the read/write data.

7.0 Pin Definition and Description

The pin definitions and descriptions are as follows:

Write Bus Signals

Pin name

Pin number

I/O

type

Description

DI[7:0]

9,8,7,6,4,3,2,

1

I

The DI pins input 8bits of data. Data input is

synchronized with the WCK clock. Data is acquired

at the rising edge of WCK clock.

WE

10

I

WE is an input signal that controls the 8bit input

data write and write pointer operation.

IE

11

I

IE is an input signal that controls the enabling/

disabling of the 8bit data input pins. The internal

write address pointer is always incremented at rising

edge of WCK by enabling WE regardless of the IE

level.

WCK

13

I

WCK is the write clock input pin. The write data

input is synchronized with this clock.

WRST

14

I

The WRST is a reset input signal that resets the

write address pointer to 0.

IRDY

15

O

IRDY is a status output flag that reports the FIFO

space availability.

*Note: For the polarity definition of all write control signals (WE, IE, WRST and IRDY), please refer

to /PLRTY pin definition and “Memory Operation” section for details.

Read Bus Signals

Pin name

Pin number

I/O

type

Description

DO[7:0]

36,37,38,39,

41,42,43,44

O

The DO pins output 8bit of data. Data output is

synchronized with the RCK clock. Data is output at

the rising edge of the RCK clock.

RE

35

I

RE is an input signal that controls the 8bit output

data read and read pointer operation.

OE

34

I

OE is an input signal that controls the enabling/

disabling of the 8bit data output pins. The internal

read address pointer is always incremented at rising

edge of RCK by enabling RE regardless of the OE

level.

RCK

32

I

RCK is the read clock input pin. The read data