AL440B

AL440B

November 28, 2001

11

Start

Slave addr = 0h Ack

Ack

Ack Stop

Index = 0Fh

Data = F0h

SDA

SCL

AL440B Serial bus Write timing

Suppose data is to be read from register 05h using read slave address 1h, the timing is as follows:

Start

Slave addr = 0h

Ack

Ack

Ack

Index = 05h

Read slave addr = 1h

SDA

SCL

AL440B Serial bus read timing

NAck

Stop

Data read cycle

Stop

Start

11.0 Memory Operation

11.1 Power-On-Reset & Initialization

During the system power on, a 200

µs negative pulse on the /RESET pin is required and will

automatically initialize chip logic. Apply a valid reset pulse to WRST and RRST after power-on-

reset to reset read/write address pointer to zero.

11.2 WRST, RRST Reset Operation

The reset signal can be given at any time regardless of the WE, RE and OE status, however, they still

need to meet the setup time and hold time requirements with reference to the clock input. When the

reset signal is provided during disabled cycles, the reset operation is not executed until cycles are

enabled again.

11.3 Control Signals Polarity Select

The AL440B provides the option for operating polarity on controlling signals. With this feature the

application design can benefit by matching up the operation polarity between AL440B and an

existing interfacing devices without additional glue logic. The operating polarity of control signals

WE, RE, WRST, RRST, IE, OE, IRDY and ORDY are controlled by /PLRTY signal. When

/PLRTY is pulled high all 8 signals will be active low. When /PLRTY is pulled low all 8 signals will

be active high.