AL440B

AL440B

November 28, 2001

12

11.4 FIFO Write Operation

In the FIFO write operation, 8 bits of write data are input in synchronization with the WCK clock.

The FIFO write operation is determined by WRST, WE, IE and WCK signals and the combination of

these signals could produce different write result. The /PLRTY signal determines the activated

polarity of these control signals. The following tables describe the WRITE functions under different

operating polarities.

/PLRTY = VDD

WRST

WE

IE

WCK Function

L

-

-

↑

Write reset.

The write pointer is reset to zero.

H

L

L

↑

Normal Write operation.

H

L

H

↑

Write address pointer increases, but no new data will be

written to memory. Old data is retained in memory.

(Write mask function)

H

H

-

↑

Write operation stopped. Write address pointer is also stopped.

/PLRTY = GND

WRST

WE

IE

WCK Function

H

-

-

↑

Write reset.

The write pointer is reset to zero.

L

H

H

↑

Normal Write operation.

L

H

L

↑

Write address pointer increases, but no new data will be

written to memory. Old data is retained in memory.

(Write mask function)

L

L

-

↑

Write operation stopped. Write address pointer is also stopped.

11.5 FIFO Read Operation

In the FIFO read operation, 8 bits of read data are available in synchronization with the RCK clock.

The access time is stipulated from the rising edge of the RCK clock. The FIFO read operation is

determined by RRST, RE, OE and RCK signals, so the combination of these signals could produce

varying read results. The /PLRTY signal could decide the activated polarity of these control signals.

The following tables describe the READ functions under different operating polarities.

/PLRTY = VDD

RRST

RE

OE

RCK Function

L

L

L

↑

Read reset. The read pointer is reset to zero.

Data in the address 0 is output.

L

L

H

↑

Read reset. The read pointer is reset to zero.

Output is high impedance.

L

H

L

↑

Read address pointer is stopped. Output data is held. Read

address pointer will be reset to zero and data in the address 0 is

output after RE goes low.