AL440B

AL440B

November 28, 2001

7

output is synchronized with this clock.

RRST

31

I

The RRST is a reset input signal that resets the read

address pointer to 0.

ORDY

30

O

ORDY is a status output flag that reports the FIFO

data availability.

*Note: For the polarity definition of all read control signals (RE, OE, RRST and ORDY), please refer

to /PLRTY pin definition and “Memory Operation” section for details.

Serial Port Bus Signals

Pin name

Pin number

I/O

type

Description

SDA

25

I/O SDA carries the serial bus read/write data bits. The

SDA data bit is valid when the SCL is high after

start up sequence.

SCL

24

I

SCL supplies the serial bus clock signal to FIFO.

The serial data bit is valid when the SCL is high

after start up sequence.

/SDAEN

23

I

/SDAEN controls the enabling/disabling of serial

bus interface. When /SDAEN is high, the serial

interface is disabled and SDA pin is high

impedance. When /SDAEN is low, the serial

interface is enabled and data can be written to or

read from the FIFO registers.

Power/Ground Signals

Pin name

Pin number

I/O

type

Description

5, 29, 40

-

3.3V

± 10%.

GND

12, 26, 33

-

Ground.

18

-

Dedicated power pin for the internal oscillator. 3.3V

± 10%.

AGND

22

-

Dedicated ground pin for the internal oscillator.

Miscellaneous Signals

Pin name

Pin number

I/O

type

Description

/RESET

27

I

The global reset pin /RESET will automatically

initialize chip logic. For the recommended circuit

for the global reset signal, please refer to the

Application Notes.