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TAS5825M Datasheet(PDF) 16 Page - Texas Instruments |
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TAS5825M Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 71 page ![]() 16 TAS5825M SLASEH7 – JANUARY 2018 www.ti.com Product Folder Links: TAS5825M Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 8.4 Device Functional Modes 8.4.1 Software Control The TAS5825M device is configured via an I2 C communication port. The I2C Communication Protocol is detailed in the I2C Communication Port section. The I2C timing requirements are described in the I2C Bus Timing – Standard and I2C Bus Timing – Fast sections. There are two methods to program TAS5825M DSP memory. Loading with I2C Communication Port by host processor or fast loading from external EEPROM with SPI communication Port. TAS525M supports to load the DSP memory data from external EEPROM via SPI. The GPIOs can be configured as SI,SO and SCK for EEPROM via Register (0x60,0x61,0x62,0x63,0x64). The chip selection CS of EEPROM is controlled by the Host Processor. For more information about EEPROM Fast boot loader, see Application note: Program TAS5825M DSP memory from external EEPROM. 8.4.2 Speaker Amplifier Operating Modes The TAS5825M device can be used with two different amplifier configurations, can be configured by Register 0x02h -D[2]: • BTL Mode • PBTL Mode 8.4.2.1 BTL Mode The familiar BTL mode of operation uses the TAS5825M device to amplify two independent signals, which represent the left and right portions of a stereo signal. The amplified left signal is presented on differential output pair shown as OUT_A+ and OUT_A-, the amplified right signal is presented on differential output pair shown as OUT_B+ and OUT_B-. 8.4.2.2 PBTL Mode The PBTL mode of operation is used to describe operation in which the two outputs of the device are placed in parallel with one another to increase the power sourcing capabilities of the device. On the output side of the TAS5825M device, the summation of the devices can be done before the filter in a configuration called Pre-Filter Parallel Bridge Tied Load (PBTL). However, the two outputs can be required to merge together after the inductor portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive inductors to be used because the current is divided between the two inductors. The process is called Post-Filter PBTL. On the input side of the TAS5825M device, the input signal to the PBTL amplifier is left frame of I2S or TDM data. 8.4.3 Device State Control Except Shutdown Mode, TAS5825M has other 4 states for different power dissipation • Register 0x03h -D[1:0]=00, Device stays in Deep Sleep Mode. In this mode, I2 C block keep works. This mode can be used to extend the battery life time in some portable speaker application case, once the host processor stopped playing audio for a long time, TAS5825M can be set to Deep Sleep Mode to minimize power dissipation until host processor start playing audio again. Device returns back to Play Mode by setting Register 0x03h -D[1:0] to 11. Compare with Shutdown Mode (Pull PDN Low), enter or exit Deep Sleep Mode, DSP keeps active. • Register 0x03h -D[1:0]=01, Device stays in Sleep Mode. In this mode, I2 C block, Digital core, DSP Memory , 5V Analog LDO keep works. Compare with Shutdown Mode (Pull PDN Low), enter or exit Sleep Mode, DSP keeps active. • Register 0x03h -D[1:0]=10, Device stays in Hiz Mode. In this mode, Only output driver set to be Hiz state, all other block work normally. • Register 0x03h -D[1:0]=11, Device stays in Play Mode. |
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