AD5590 datasheet(32/45 Pages) AD

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AD5590

Rev. A | Page 31 of 44

DSYNC Interrupt

In a normal write sequence, the DSYNCx line is kept low for

32 falling edges of DSCLK, and the DAC is updated on the 32nd

falling edge and rising edge of DSYNCx. However, if DSYNCx is

brought high before the 32nd falling edge, this acts as an interrupt

to the write sequence. The shift register is reset, and the write

sequence is seen as invalid. Neither an update of the DAC

(see Figure 63).

DAC Internal Reference Register

The on-board references in the DAC blocks are off at power-up

by default. This allows the use of an external reference if the

application requires it. The on-board references can be turned

on or off by a user-programmable internal REF register by

setting Bit DB0 high or low (see Table 13). Command 1000 is

reserved for setting the internal REF register (see Table 11).

DAC Power-On Reset

The DAC blocks contain a power-on reset circuit that controls

the output voltage during power-up. The DAC outputs power

up to 0 V. The output remains powered up at this level until a

valid write sequence is made to the DAC. This is useful in appli-

cations where it is important to know the state of the output of

the DAC while it is in the process of powering up. There is also

a software executable reset function that resets the DAC to the

power-on reset code. Command 0111 is reserved for this reset

function (see Table 11). Any events on LDAC or CLR during

power-on reset are ignored.

DAC Power-Down Modes

The DAC block contains four separate modes of operation.

Command 0100 is reserved for the power-down function (see

Table 11). These modes are software-programmable by setting

Bit DB9 and Bit DB8 in the control register.

Table 15 shows how the state of the bits corresponds to the mode

of operation of the device. Any or all DACs (DAC0 to DAC7 in

Block 1 or DAC8 to DAC15 in Block 2) can be powered down to

the selected mode by setting the corresponding eight bits to 1. See

Table 16 for the contents of the input shift register during power-

down/power-up operation. When using the internal reference,

only all channel power-down to the selected modes is supported.

When both bits are set to 0, each block works normally with its

normal power consumption of 1.3 mA at 5 V. However, for the

three power-down modes, the supply current of each block falls

to 0.4 µA at 5 V. Not only does the supply current fall, but the

output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the

advantage that the output impedance of the DAC is known

while it is in power-down mode. There are three different

options. The output is connected internally to GND through

either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited

(three-state). The output stage is illustrated in Figure 62.

RESISTOR

NETWORK

VOUT

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 62. Output Stage During Power-Down

DSCLK

DDIN

DB31

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 32ND FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 32ND FALLING EDGE

DB31

DB0

DSYNCx

Figure 63. SYNC Interrupt Facility

Table 13. DAC Internal Reference Register

Internal REF Register (DB0)

Action

Reference off (default)

Reference on

Table 14. DAC 32-Bit Input Shift Register Contents for Reference Setup Command

MSB

LSB

DB31 to DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19 to DB1

DB0

1/0

Don’t care

Command bits (C3 to C0)

Address bits (A3 to A0)—don’t care

Don’t care

Internal REF register

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