AD5590 datasheet(29/45 Pages) AD

29 / 45 page

AD5590

Rev. A | Page 28 of 44

ADC Transfer Function

The output coding of the ADC is either straight binary or twos

complement, depending on the status of the LSB (range bit) in

the ADC control register. The designed code transitions occur

midway between successive LSB values (that is, 1 LSB, 2 LSBs,

and so on). The LSB size is equal to VREFA/4096. The ideal transfer

characteristic for the ADC when straight binary coding is selected

is shown in Figure 57.

111...111

111...110

111...000

000...010

011...111

000...001

000...000

1LSB

+VREF – 1LSB

1LSB = VREF/4096

VREF IS EITHER VREFA OR 2 × VREFA

ANALOG INPUT

Figure 57. Straight Binary Transfer Characteristic

011...111

011...110

000...001

000...000

111...111

100...010

100...001

100...000

+VREFA – 1LSB

–VREFA + 1LSB

1LSB = 2 × VREFA/4096

VREFA – 1LSB

ANALOG INPUT

Figure 58. Twos Complement Transfer Characteristic with

VREFA ± VREFA Input Range

Analog Input Selection

Any one of 16 analog input channels can be selected for conversion

by programming the multiplexer with the ADD3 to ADD0

address bits in the ADC control register. The channel configura-

tions are shown in Table 23. The ADC can also be configured to

automatically cycle through a number of channels as selected.

The sequencer feature is accessed via the SEQ and shadow bits

in the ADC control register (see Table 21). The ADC can be

programmed to continuously convert on a selection of channels

in ascending order. The analog input channels to be converted

on are selected through programming the relevant bits in the

shadow register (see Table 26). The next serial transfer then acts

on the sequence programmed by executing a conversion on the

lowest channel in the selection.

The next serial transfer results in a conversion on the next

highest channel in the sequence, and so on. It is not necessary

to write to the ADC control register once a sequencer operation

has been initiated. The write bit must be set to 0 to ensure

the ADC control register is not accidentally overwritten, or

the sequence operation interrupted. If the ADC control register

is written to at any time during the sequence, then it must be

ensured that the SEQ and shadow bits are set to 1 and 0,

respectively to avoid interrupting the automatic conversion

sequence. This pattern continues until the ADC is written to

and the SEQ and shadow bits are configured with any bit

combination except 1, 0. On completion of the sequence, the

ADC sequencer returns to the first selected channel in the shadow

Rather than selecting a particular sequence of channels, a number

of consecutive channels beginning with Channel 0 can also be

programmed via the control register alone, without needing

to write to the shadow register. This is possible if the SEQ and

shadow bits are set to 1, 1. The channel address bits, ADD3

through ADD0, then determine the final channel in the consec-

utive sequence. The next conversion is on Channel 0, then

Channel 1, and so on until the channel selected via the ADD3

through ADD0 address bits is reached. The cycle begins again

on the next serial transfer provided the write bit is set to low

or, if high, that the SEQ and shadow bits are set to 1, 0; then,

the ADC continues its preprogrammed automatic sequence

uninterrupted. Regardless of which channel selection method

is used, the 16-bit word output from the ADC during each

conversion always contains the channel address that the conver-

sion result corresponds to, followed by the 12-bit conversion

result (see the Serial Interface section).

Digital Inputs

The digital inputs applied to the ADC are not limited by the

maximum ratings that limit the analog inputs. Instead, the

digital inputs applied can go to 7 V and are not restricted

by the ADCVDD + 0.3 V limit found on the analog inputs.

Another advantage of ASCLK, ADIN, and ASYNC not being

restricted by the ADCVDD + 0.3 V limit is the fact that power

supply sequencing issues are avoided. If ASYNC, ADIN, or

ASCLK is applied before ADCVDD, there is no risk of latch-up

as there would be on the analog inputs if a signal greater than

0.3 V was applied prior to ADCVDD.

VDRIVE

The ADC has the VDRIVE feature, which controls the voltage at

which the serial interface operates. VDRIVE allows the ADC to

easily interface to both 3 V and 5 V processors. For example, if

the ADC is operated with a VDD of 5 V, the VDRIVE pin could be

powered from a 3 V supply. The ADC has better dynamic perfor-

mance with a VDD of 5 V while still being able to interface to 3 V

processors. Care should be taken to ensure that VDRIVE does not

exceed ADCVDD by more than 0.3 V (see the Absolute Maximum

Ratings section).

AD5590 Datasheet(PDF) 29 Page - Analog Devices

AD5590 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL