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AD9671EBZ Datasheet(PDF) 31 Page - Analog Devices

Part # AD9671EBZ
Description  Octal Ultrasound AFE with Digital Demodulator
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9671EBZ Datasheet(HTML) 31 Page - Analog Devices

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AD9671
Data Sheet
Rev. A| Page 30 of 60
Table 14. JESD204B Parameters
Parameter
Description
AD9671 Value
S
Samples transmitted per single converter per frame cycle
1
M
Number of converters per converter device
8 with demodulator/decimator disabled, 16 with
demodulator/decimator enabled
L
Number of lanes per converter device
1, 2, or 4
N
Converter resolution
12, 14, or 16
N’
Total number of bits per sample
16
CF
Number of control words per frame clock cycle per
converter device
0
CS
Number of control bits per conversion sample
0
K
Number of frames per multiframe
Configurable on the AD9671
HD
High density mode
0
F
Octets per frame
4, 8, 16, or 32 (dependent on L = 4, 2, or 1, respectively)
C
Control bit
0
T
Tail bit
Available on the AD9671
SCR
Scrambler enable/disable
Configurable on the AD9671
FCHK
Checksum for the JESD204B parameters
Automatically calculated and stored in the register map
OUTPUT
SAMPLES
FROM CHANNEL
TRANSPORT
LAYER
DATA LINK
LAYER
PHYSICAL
LAYER
SCRAMBLER
SERIALIZER
FRAME
CONSTRUCTION
8B/10B
ENCODER
SAMPLE
CONSTRUCTION
LANE
ALIGNMENT
CHARACTER
GENERATION
Figure 45. AD9671 Transmit Link Simplified Block Diagram
Figure 45 shows a simplified block diagram of the AD9671
JESD204B link. By default, the AD9671 is configured to use
eight channels and four lanes. Channel A and Channel B data
is output to SERDOUT1±, Channel C and Channel D data is
output to SERDOUT2±, Channel E and Channel F data is
output to SERDOUT3±, and Channel G and Channel H data
is output to SERDOUT4±. The AD9671 allows other configura-
tions such as combining the outputs of the eight channels onto a
single lane.
By default in the AD9671, the 14-bit converter word from each
converter is broken into two octets (eight bits of data). Bit 0
(MSB) through Bit 7 are in the first octet. The second octet
contains Bit 8 through Bit 13 (LSB) and two tail bits. The tail
bits can be configured as zeros or a pseudorandom number
sequence.
The two resulting octets can be scrambled. Scrambling is optional
but is available to avoid spectral peaks when transmitting similar
digital data patterns. The scrambler uses a self synchronizing
polynomial-based algorithm defined by the equation: 1 + x14 +
x15. The descrambler in the receiver must be a self synchronizing
version of the scrambler polynomial.
The two octets are then encoded with an 8B/10B encoder. The
8B/10B encoder works by taking eight bits of data (an octet) and
encoding them into a 10-bit symbol. Figure 46 shows how the
14-bit data is taken from the ADC, the tail bits are added, the two
octets are scrambled, and how the octets are encoded into two
10-bit symbols. Figure 46 illustrates the default data format.
At the data link layer, in addition to the 8B/10B encoding, the
character replacement allows the receiver to monitor frame
alignment. The character replacement process occurs on the
frame and multiframe boundaries, and implementation depends
on which boundary is occurring and if scrambling is enabled.
If scrambling is disabled, the following applies. If the last
scrambled octet of the last frame of the multiframe equals the
last octet of the previous frame, the transmitter replaces the last
octet with the control character /A/ = /K28.3/. On other frames
within the multiframe, if the last octet in the frame equals the
last octet of the previous frame, the transmitter replaces the last
octet with the control character /F/ = /K28.7/.
If scrambling is enabled, the following applies. If the last octet of
the last frame of the multiframe equals 0x7C, the transmitter
replaces the last octet with the control character /A/ = /K28.3/.
On other frames within the multiframe, if the last octet equals
0xFC, the transmitter replaces the last octet with the control
character /F/ = /K28.7/.
Refer to JEDEC Standard JESD204B (July 2011) for additional
information about the JESD204B interface. Section 5.1
describes the transport layer and data format details, and
Section 5.2 describes scrambling and descrambling.



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