AD9671EBZ datasheet(39/61 Pages) AD

39 / 61 page

AD9671

Data Sheet

Rev. A| Page 38 of 60

SDIO Pin

The SDIO pin is required to operate the SPI. The SDIO pin has

an internal 30 kΩ pull-down resistor that pulls it low and is only

1.8 V tolerant. To drive the SDIO pin from a 3.3 V logic level, insert

a 1 kΩ resistor in series with this pin to limit the current.

SCLK Pin

The SCLK pin is required to operate the SPI. The SCLK pin has

an internal 30 kΩ pull-down resistor that pulls it low and is only

1.8 V tolerant. To drive the SCLK pin from a 3.3 V logic level,

insert a 1 kΩ resistor in series with this pin to limit the current.

CSB Pin

The CSB pin is required to operate the SPI. The CSB pin has an

internal 70 kΩ pull-up resistor that pulls it high and is only 1.8 V

tolerant. To drive the CSB pin from a 3.3 V logic level, insert a

1 kΩ resistor in series with this pin to limit the current.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor

nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a

resistor other than the recommended 10.0 kΩ resistor for RBIAS

degrades the performance of the device. Therefore, use at least a

1% tolerance on this resistor to achieve consistent performance.

VREF Pin

A stable and accurate 0.5 V voltage reference is built into the

AD9671. This voltage reference is amplified internally by a factor of

2, setting VREF to 1.0 V, which results in a full-scale differential

input span of 2.0 V p-p for the ADC. VREF is set internally by

default, but the user can drive the VREF pin externally with a

1.0 V reference to achieve more accuracy. However, the AD9671

does not support ADC full-scale ranges less than 2.0 V p-p.

When applying the decoupling capacitors to the VREF pin, use

ceramic, low equivalent series resistance (ESR) capacitors. Ensure

that these capacitors are near the reference pin and on the same

layer of the PCB as the AD9671. The VREF pin must have both

a 0.1 μF capacitor and a 1 μF capacitor that are connected in

parallel to analog ground. These capacitor values are recommended

for the ADC to properly settle and acquire the next valid sample.

GPOx Pins

Use the general-purpose output pins, GPO0, GPO1, GPO2, and

GPO3, in a system to provide programmable inputs to other chips

in the system. The value of each pin is set via Address 0x00E to

either Logic 0 or Logic 1 (see Table 33).

ADDRx Pins

Use the chip address pins to address individual AD9671 devices in

a system. Chip address mode is enabled using Address 0x115,

Bit 5 (see Table 33). If the value written to Bits[4:0] matches the

value on the chip address bit pins (ADDR4 to ADDR0), the device

is selected and any subsequent SPI writes or reads to addresses

indicated as chip registers are written only to that device. If chip

address mode is disabled, write all addresses regardless of the value

on the address pins.

TX_TRIG± Pins

The TX_TRIG± function has several uses within the AD9671

and is initiated with an external hardware trigger either on the TX_

TRIG± pins or by a software trigger by setting Address 0x10C, Bit 5

to 1. The hardware trigger has the advantage of guaranteed

synchronous triggering of multiple AD9671 devices in a system.

The setup and hold time for each TX_TRIG± hardware input is

given in Table 3 as 1 ns. Due to the asynchronous SPI function,

the software trigger cannot guarantee synchronization of multiple

AD9671 devices. If the TX_TRIG± hardware trigger is not used,

tie the TX_TRIG± pins in a low logic state.

The TX_TRIG± function is used to reset circuits in the digital

demodulator and decimator (see the Baseband Demodulator

and Decimator section), initiate the advanced power mode (see

the Advanced Power Control section), and synchronize the data

serialization in the JESD204B block (see the JESD204B

Overview section).

ANALOG TEST TONE GENERATION

The AD9671 can generate analog test tones that the user can

then switch to the input of the LNA of each channel for channel

gain calibration. The test tone amplitude at the LNA output is

dependent on LNA gain, as shown in Table 23.

Table 23. Test Signal Fundamental Amplitude at LNA Output

Address 0x116[3:2],

Analog Test Tones

LNA Gain

15.6 dB

LNA Gain

17.9 dB

LNA Gain

21.6 dB

00 (default)

80 mV p-p

98 mV p-p

119 mV p-p

160 mV p-p

196 mV p-p

238 mV p-p

320 mV p-p

391 mV p-p

476 mV p-p

Reserved

Calculate the test signal amplitude at the input to the ADC

given the LNA gain, attenuator control voltage, and the PGA

gain. Table 24 and Table 25 list example calculations.

Table 24. Test Signal Fundamental Amplitude at ADC Input,

VGAIN = 0 V, PGA Gain = 21 dB

Address 0x116[3:2],

Analog Test Tones

LNA Gain

15.6 dB

LNA Gain

17.9 dB

LNA Gain

21.6 dB

00 (default)

−29 dBFS

−28 dBFS

−26 dBFS

−23 dBFS

−22 dBFS

−20 dBFS

−17 dBFS

−16 dBFS

−14 dBFS

Reserved

Table 25. Test Signal Fundamental Amplitude at ADC Input,

VGAIN = 0 V, PGA Gain = 30 dB

Address 0x116[3:2],

Analog Test Tones

LNA Gain

15.6 dB

LNA Gain

17.9 dB

LNA Gain

21.6 dB

00 (default)

−20 dBFS

−19 dBFS

−17 dBFS

−14 dBFS

−13 dBFS

−11 dBFS

−8 dBFS

−7 dBFS

−5 dBFS

Reserved

AD9671EBZ Datasheet(PDF) 39 Page - Analog Devices

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