AD9671EBZ datasheet(41/61 Pages) AD

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AD9671

Data Sheet

Rev. A| Page 40 of 60

DIGITAL DEMODULATOR/DECIMATOR

The AD9671 contains digital processing capability. Each

channel has three stages of processing that are available: RF

decimator, baseband (BB) demodulator, and baseband

decimator. For test purposes, the input to the demodulator/

decimator can serve as a test waveform. Normally, the input is

the output of the ADC. The output of the demodulator/decimator

is sent to the framer/serializer for output formatting.

The maximum data rate of the BB demodulator and decimator

is 65 MSPS. Therefore, if the sample of the ADC is greater than

65 MSPS, enable the RF decimator (fixed rate of 2). The ADC

resolution is 14 bits. The maximum resolution at the output of

the digital processing is 16 bits. Saturation of the ADC is

determined after the dc offset calibration to ensure maximum

dynamic range. Depending on decimation rate, the loss in

output SNR due to truncation to 16 bits is negligible.

VECTOR PROFILE

To minimize the time needed to reconfigure device settings

during operation, the device supports configuration profiles.

The user can store up to 32 profiles in the device. A profile is

selected by a 5-bit index. A profile consists of a 64-bit vector, as

described in Table 27. Each parameter is concatenated to form the

64-bit profile vector. The profile memory starts at Register 0xF00

and ends at Register 0xFFF. Write the memory in either stream

or address selected data mode. However, the user must read the

memory using stream mode. When writing or reading in

stream mode while the SPI configuration is set to MSB first

mode (default setting for Register 0x000), the write/read address

needs to refer to the last register address, not the first one. For

example, when writing or reading the first profile that spans the

address space between Register 0xF00 and Register 0xF07, with the

SPI port configured as MSB first, the referenced address must

be Register 0xF07 to allow reading or writing the 64 profile bits

in MSB mode. For more information about stream mode, see

the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI.

There is a buffer used to store the current profile data. When

the profile index is written in Register 0x10C, the selected profile is

read from memory and stored in the current profile buffer. The

profile memory is read/written in the SPI clock domain. After

the SPI writes the profile index value, it takes four SPI clock

cycles to read the profile from RAM and store it in the current

profile buffer. If the SPI is in LSB mode, these additional SPI

clock cycles are provided when the profile index register is

written. If the SPI is in MSB mode, an additional byte must be

read or written to update the profile buffer.

Updating profile memory does not affect the data in the profile

buffer. The profile index register must be written to cause a

refresh of the current profile data, even if the profile index

ADC OUTPUT OR

TEST WAVEFORM

DC OFFSET

CALIBRATION

MULTIBAND AAF

DECIMATE BY 2

NUMERICALLY

CONTROLLED

OSCILLATOR

RF DECIMATOR

FRAMER

SERIALIZER

HIGH-PASS

FILTER

–Sin

Cos

BB DECIMATOR

BB DEMODULATOR

LOW-PASS

FILTER

DECIMATOR

LOW-PASS

FILTER

DECIMATOR

Figure 56. Simplified Block Diagram of a Single Channel of Demodulator/Decimator

Table 27. Profile Definition

Field

No. of

Bits

Description

Demodulation frequency (fD)

fD = f × fSAMPLE/216, where (f ) = [0,(216 − 1)] and fSAMPLE is the effective sample rate

0x0000: fD = 0 (dc, I = cos(0) = 1, Q = sin(0) = 0)

0x0001: fD = fSAMPLE/216

…

0x8000: fD = fSAMPLE/2

…

0xFFFF (216 − 1): fD = fSAMPLE (216 − 1)/216 = −fSAMPLE/216

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