AD9671EBZ datasheet(45/61 Pages) AD

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AD9671

Data Sheet

Rev. A| Page 44 of 60

SERIAL PORT INTERFACE (SPI)

The AD9671 SPI allows the user to configure the signal chain for

specific functions or operations through the structured register

space provided inside the chip. The SPI offers the user added

flexibility and customization, depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the port. Memory is organized into bytes that

can be further divided into fields, as documented in the Memory

Map section. For detailed operational information, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

Three pins define the serial port interface: SCLK, SDIO, and CSB

(see Table 30). The SCLK (serial clock) pin synchronizes the read

and write data presented to the device. The SDIO (serial data

input/output) pin is a dual-purpose pin that allows data to be

sent to and read from the internal memory map registers of the

device. The CSB (chip select bar) pin is an active low control that

enables or disables the read and write cycles.

Table 30. Serial Port Pins

Function

SCLK

Serial clock. Serial shift clock input. SCLK

synchronizes serial interface reads and writes.

SDIO

Serial data input/output. Dual-purpose pin that

typically serves as an input or an output, depending

on the instruction sent and the relative position in

the timing frame.

CSB

Chip select bar (active low). This control gates the

read and write cycles.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing sequence. During the

instruction phase, a 16-bit instruction is transmitted, followed

by one or more data bytes, which is determined by Bit Field W0

and Bit Field W1. An example of the serial timing and its

definitions are shown in Figure 61 and Table 31.

During normal operation, CSB signals to the device that SPI

commands are to be received and processed. When CSB is

brought low, the device processes SCLK and SDIO to execute

instructions. Normally, CSB remains low until the communication

cycle is complete. However, if connected to a slow device, CSB

can be brought high between bytes, allowing older microcontrollers

enough time to transfer data into shift registers. CSB can be

stalled when transferring one, two, or three bytes of data. When

W0 and W1 are set to 11, the device enters streaming mode and

continues to process data, either reading or writing, until CSB is

taken high to end the communication cycle. CSB being high allows

complete memory transfers without the need for additional

instructions. Regardless of the mode, if CSB is taken high in the

middle of a byte transfer, the SPI state machine is reset, and the

device waits for a new instruction.

The SPI port can be configured to operate in different manners.

CSB can also be tied low to enable 2-wire mode. When CSB is

tied low, SCLK and SDIO are the only pins required for

communication. Although the device is synchronized during

power-up, exercise caution when using 2-wire mode to ensure

that the serial port remains synchronized with the CSB line.

When operating in 2-wire mode, use a 1-, 2-, or 3-byte transfer

exclusively. Without an active CSB line, streaming mode can be

entered but not exited.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a read-

back operation, performing a readback causes the serial data

input/output (SDIO) pin to change direction from an input to

an output at the appropriate point in the serial frame.

The user can send data in MSB first mode or LSB first mode.

MSB first mode is the default at power-up and is changed by

adjusting the configuration register (Address 0x000). For more

information about this and other features, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

HARDWARE INTERFACE

The pins described in Table 30 constitute the physical interface

between the programming device and the serial port of the

AD9671. The SCLK and CSB pins function as inputs when

using the SPI. The SDIO pin is bidirectional, functioning as an

input during write phases and as an output during readback.

If multiple SDIO pins share a common connection, ensure that

proper VOH levels are met. Figure 60 shows the number of SDIO

pins that can be connected together and the resulting VOH level,

assuming the same load for each AD9671.

NUMBER OF SDIO PINS CONNECTED TOGETHER

1.715

1.720

1.725

1.730

1.735

1.740

1.745

1.750

1.755

1.760

1.765

1.770

1.775

1.780

1.785

1.790

1.795

1.800

030

100

Figure 60. SDIO Pin Loading

This interface is flexible enough to be controlled either by serial

programmable read only memories (PROMs) or by PIC

microcontrollers, which provide the user with an alternative to a

full SPI controller for programming the device (see the AN-812

Application Note, Microcontroller-Based Serial Port Interface

(SPI®) Boot Circuit).

AD9671EBZ Datasheet(PDF) 45 Page - Analog Devices

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