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AD9671EBZ Datasheet(PDF) 8 Page - Analog Devices |
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AD9671EBZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 61 page  Data Sheet AD9671 Rev. A| Page 7 of 60 Parameter1 Test Conditions/Comments Min Typ Max Unit ADC Resolution 14 Bits SNR 75 dB ADC REFERENCE Output Voltage Error VREF = 1 V ±50 mV Load Regulation at 1.0 mA VREF = 1 V 2 mV Input Resistance 7.5 kΩ 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 The overrange condition is specified as 6 dB more than the full-scale input range. 3 The internal LO frequency, fLO, is generated from the supplied multiplier local oscillator frequency, fMLO, by dividing it up by a configurable divider value (M) that can be 4, 8, or 16; the MLO signal is named 4LO, 8LO, or 16LO, accordingly. 4 Baseband decimation rate = 4. M = 16. |
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