TUSB1210 datasheet(56/66 Pages) TI1

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TUSB1210

SLLSE09H – NOVEMBER 2009 – REVISED JUNE 2015

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6.4

Layout

6.4.1

Layout Guidelines

•

The VDDIO pins of the TUSB1210 supply 1.8-V (nominal) power to the core of the TUSB1210. This

power rail can be isolated from all other power rails by a ferrite bead to reduce noise.

•

The VBAT pin of the TUSB1210 supply 3.3-V (nominal) power rail to the TUSB1210. This power rail can

be isolated from all other power rails by a ferrite bead to reduce noise.

•

The VBUS pin of the TUSB1210 supply 5-V (nominal) power rail to the TUSB1210. This pin is normally

connected to the VBUS pin of the USB connector.

•

All power rails require 0.1

μF decoupling capacitors for stability and noise immunity. The smaller

decoupling capacitors should be placed as close to the TUSB1210 power pins as possible with an

optimal grouping of two of differing values per pin.

6.4.1.1

Ground

It is recommended that almost one board ground plane be used in the design. This provides the best

image plane for signal traces running above the plane. An earth or chassis ground is implemented only

near the USB port connectors on a different plane for EMI and ESD purposes.

6.4.2

Layout Example

Figure 6-5. TUSB1210 Layout Example

Application, Implementation, and Layout

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TUSB1210 Datasheet(PDF) 56 Page - Texas Instruments