SSD1852 datasheet(28/55 Pages) ETC

28 / 55 page

SSD1852

Rev 1.0

01/2003

SOLOMON

Bit Pattern

Command

Description

1000 0011

OTP programming

This command start program LCD driver with OTP offset

value. This command only execute once. No effect on the

second run. Detail of OTP programming procedure on

page 30.

1111 0100

0000 0X010

Enable DMA mode

This command enable /disable the Direct Memory Access

mode .

1000 0100

0A6A5A4 A3A2A1A0

0000 B3B2B1B0

0C6C5C4 C3C2C1C0

0000 D3D2D1D0

Set Start/End Column

and Page address in

DMA mode

This command set the start column address (A6~A0), end

column address (C6~C0), start page address (B3~B0) and

end page address (D3~D0) in DMA mode. The page and

column address should be follow the below rule.

Min. value

Max value

A6~A0

0000000

C6~C0

B3~B0

0000

D3~D0

C6~C0

A6~A0

1111111

D3~D0

B3~B0

1111

Remarks: this command is available only when DMA mode

is enabled.

1111 1101

0001 0X010

Lock / Unlock

Interface

X0= 0 : Lock the IC. The driver ignores all command and

data written, except the unlock command or pin reset.

X0 = 1 : Unlock the IC. The driver accepts any command

and data written.

Read Status Byte (D/ C = 0, R/W( WR ) = 1, E( RD ) = 1)

An 8 bits status byte will be placed onto the data bus when a read operation is performed if D/ C is low. The status

byte is defined as follows:

Bit Pattern

Command

Description

BUSY ON RES MF2 MF1 MF0 DS1

DS0

Read Display Status

BUSY

0: Chip is idle

1: Chip is executing instruction

0: Display is OFF

1: Display is ON

RES

0: Chip is idle

1: Chip is executing reset

MF2- MF0 : 010

DS1, DS0 : Display size

Data Read / Write (D/ C = 1, R/W( WR ) = 1, E( RD ) = 1)

To read data from the GDDRAM, input High to R/W( WR ) pin and D/ C pin for 6800-series parallel mode,

Low to E( RD ) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided for serial mode. In

normal mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a

dummy read is required before the first data is read. See

Figure 3 in Functional Description.

To write data to the GDDRAM, input Low to R/W( WR ) pin and High to D/ C pin for 6800-series parallel mode. For

serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one

automatically after each data write. The address will be reset to 0 in execution of next data read/write operation when

it is 127.

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