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HT45F77 Datasheet(PDF) 51 Page - Holtek Semiconductor Inc |
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HT45F77 Datasheet(HTML) 51 Page - Holtek Semiconductor Inc |
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51 / 203 page  Rev. 1.20 50 De�e��e� 1�� 201� Rev. 1.20 51 De�e��e� 1�� 201� HT45F77 Body Fat Scale Flash MCU HT45F77 Body Fat Scale Flash MCU Bit3 LTO:Lowspeedsystemoscillatorreadyflag 0:Notready 1:Ready Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeed systemoscillatorisstableafterpoweronresetorawake-uphasoccurred.Theflag willbelowwhenintheSLEEP0Modebutafterawake-uphasoccurred,theflagwill changetoahighlevelafter1024clockcyclesiftheLXToscillatorisusedand1~2 clockcyclesiftheLIRCoscillatorisused. Bit2 HTO:Highspeedsystemoscillatorreadyflag 0:Notready 1:Ready Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeed systemoscillatorisstable.Thisflagisclearedtozerobyhardwarewhenthedeviceis poweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable. Thereforethisflagwillalwaysbereadas"1"bytheapplicationprogramafterdevice power-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterawake- uphasoccurred,theflagwillchangetoahighlevelafter1024clockcyclesiftheHXT oscillatorisusedandafter15~16clockcyclesiftheHIRCoscillatorisused. Bit1 IDLEN:IDLEModecontrol 0:Disable 1:Enable ThisistheIDLEModeControlbitanddetermineswhathappenswhentheHALT instructionisexecuted.Ifthisbitishigh,whenaHALTinstructionisexecutedthe devicewillentertheIDLEMode.IntheIDLE1ModetheCPUwillstoprunning butthesystemclockwillcontinuetokeeptheperipheralfunctionsoperational,if FSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstop inIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALT instructionisexecuted. Bit0 HLCLK:systemclockselection 0:fH/2~fH/64orfSUB 1:fH ThisbitisusedtoselectifthefHclockorthefH/2~fH/64orfSUBclockisusedas thesystemclock.WhenthebitishighthefHclockwillbeselectedandiflowthe fH/2~fH/64orfSUBclockwillbeselected.WhensystemclockswitchesfromthefH clocktothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconserve power. CTRL Register Bit 7 6 5 4 3 2 1 0 Na�e FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 "x" unknown Bit7 FSYSON:fSYSControlinIDLEMode 0:Disable 1:Enable Bit6~3 Unimplemented,readas"0" Bit2 LVRF:LVRfunctionresetflag Describedelsewhere. Bit1 LRF:LVRControlregistersoftwareresetflag Describedelsewhere. Bit0 WRF:WDTControlregistersoftwareresetflag Describedelsewhere. |
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