ADF7011 datasheet(16/24 Pages) AD

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ADF7011

Digital Lock Detect

Digital lock detect is active high. The lock detect circuit is con-

tained at the PFD. When the phase error on five consecutive

cycles is less than 15 ns, lock detect is set high. Lock detect

remains high until 25 ns phase error is detected at the PFD.

Since no external components are needed for digital lock detect,

it is more widely used than analog lock detect.

Analog Lock Detect

This N-channel open-drain lock detect should be operated with

an external pull-up resistor of 10 k

Ω nominal. When lock has been

detected, this output will be high with narrow low-going pulses.

Voltage Regulator

The ADF7011 requires a stable voltage source for the VCO and

modulation blocks. The on-board regulator provides 2.2 V

using a band gap reference. A 2.2

µF capacitor from C

REG to

ground is used to improve stability of the regulator over a sup-

ply ranging from 2.3 V to 3.6 V. The regulator consumes less

than 400

µA and can only be powered down using the chip

enable (CE) pin. Bringing CE low disables the regulator and

also erases all values held in the registers. The serial interface

operates off the regulator supply; therefore, to write to the part,

the user must have CE high. Regulator status can be monitored

using the Regulator Ready signal from MUXOUT.

Loop Filter

The loop filter integrates the current pulses from the charge

pump to form a voltage that tunes the output of the VCO to the

desired frequency. It also attenuates spurious levels generated

by the PLL. A typical loop filter design is shown in Figure 6.

CHARGE

PUMP OUT

VCO

Figure 6. Typical Loop Filter Configuration––Third

Order Integrator

In FSK, the loop should be designed so that the loop bandwidth

(LBW) is approximately five times the data rate. Widening

the LBW excessively reduces the time spent jumping between

frequencies but may cause insufficient spurious attenuation.

For ASK systems, the wider the loop BW the better. The sud-

den large transition between two power levels will result in VCO

pulling and can cause a wider output spectrum than is desired.

By widening the loop BW to >10 times the data rate, the amount

of the VCO pulling is reduced since the loop will quickly settle

back to the correct frequency. The wider LBW may restrict the

output power and data rate of ASK based systems, compared

with FSK based systems.

Narrow-loop bandwidths may result in the loop taking long

periods of time to attain lock. Careful design of the loop filter is

critical in obtaining accurate FSK/GFSK modulation.

For GFSK, it is recommended that an LBW of 2.0 to 2.5 times

the data rate be used to ensure sufficient samples are taken of

the input data while filtering system noise.

REGULATOR READY

DIGITAL LOCK DETECT

ANALOG LOCK DETECT

R COUNTER/2 OUTPUT

N COUNTER/2 OUTPUT

R COUNTER OUTPUT

N COUNTER OUTPUT

MUX

CONTROL

MUXOUT

DGND

DVDD

Figure 5. MUXOUT Stage

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