ADF7011 datasheet(17/24 Pages) AD

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ADF7011

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Voltage Controlled Oscillator (VCO)

An on-chip VCO is included on the transmitter. The VCO con-

verts the control voltage generated by the loop filter into an output

frequency that is sent to the antenna via the power amplifier

(PA). The VCO has a typical gain of 80 MHz/V and operates

from 866 MHz to 870 MHz. The PD1 bit in the function regis-

ter is the active high bit that turns on the VCO. A frequency

divided by 2 is included to allow operation in the lower 450 MHz

band. To enable operation in the lower band, the V1 bit in the

N Register should be set to 1.

The VCO needs an external 220 nF between the VCO and the

regulator to reduce internal noise.

MUX

VCO SELECT BIT

TO PA AND

N DIVIDER

DIVIDE

BY 2

VCO CONTROL BIT

LOOP FILTER

CREG PIN

220nF

VCO

Figure 7. Voltage Controlled Oscillator

RF Output Stage

The RF output stage consists of a DAC with a number of cur-

rent sources to adjust the output power level. To set up the

power level

• FSK GFSK: The output power is set using the modulation

two MSBs set the range of the output stage, while the five

LSBs set the output power in the selected range.

• ASK: The output power as set up for FSK is the output

power for a TxDATA of 1. The output power for a zero

data bit is set up the same way but using Bits D1–D7.

The output stage is powered down by setting Bit PD2 in the

function register to zero.

P7, P6

HIGH

MED

LOW

Figure 8. Output Stage

Serial Interface

The serial interface allows the user to program the four 24-bit

registers using a 3-wire interface (CLK, Data, and Load Enable).

The serial interface consists of a level shifter, a 24-bit shift regis-

ter, and four latches. Signals should be CMOS compatible. The

serial interface is powered by the regulator, and therefore is

inactive when CE is low.

Table I. C2, C1 Truth Table

Data Latch

R Register

N Register

Modulation Register

Function Register

Data is clocked into the shift register, MSB first, on the rising

edge of each clock (CLK). Data is transferred to one of four

latches on the rising edge of LE. The destination latch is deter-

mined by the value of the two control bits (C2 and C1). These

are the two LSBs, DB1 and DB0, as shown in the timing dia-

gram of Figure 1.

VDD

RFOUT

Figure 9. Output Stage Matching

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