ADF7011 datasheet(18/24 Pages) AD

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REV. 0

–18–

ADF7011

16 – j33

868MHz

5.00

1.00

0.50

0.20

0.00

0.0

0.20

0.50

1.00

2.00

100

110

120

130

140

150

2.00

5.00

25 – j2.6

433MHz

Figure 10. Output Impedance on Smith Chart

Fractional-N

N Counter and Error Correction

The ADF7011 consists of a 15-bit

fractional-N divider.

The N Counter divides the output frequency to the output

stage back to the PFD frequency. It consists of a prescaler,

integer, and fractional part.

The prescaler can be 4/5 or 8/9. A prescaler setting of 8/9 is

recommended for 868 MHz operation. A prescaler setting of

4/5 is recommended for 433 MHz operation.

The output frequency of the PLL is

PFD Frequency

Int

Fractional

Error

×+

()+













INTEGER-N

FRACTIONAL-N

REFERENCE IN

THIRD ORDER

- MODULATOR

PFD/

CHARGE

PUMP

VCO

Figure 11. Fractional-N PLL

Fractional-N Registers

The fractional part is made up of a 15-bit divide, made up of a

12-bit N value in the N register summed with a 10-bit value

(plus sign bit) in the R register that is used for error correction,

as shown in Figure 12.

M12 M11 M10

M7M6

M5M4

M3M2

12-BIT N VALUE

F10

F7F6

F5F4

10-BIT (

SIGN) ERROR CORRECTION

N14

N13

N12

N11

N10

15-BIT FRACTIONAL N REGISTER

Figure 12. Fractional Components

The resolution of each register is the smallest amount that the

output frequency can be changed by changing the LSB of the

Changing the Output Frequency

The fractional part of the N register changes the output fre-

quency by

PFD Frequency

Fractional

gister Value

The frequency error correction contained in the R register

changes the output frequency by

PFD Frequency

Error Correction

gister Value

By default, this will be set to 0. The user can calibrate the system

and set this by writing a twos complement number to Bits F1–F11

in the R register. This can be used to compensate for initial error,

temperature drift, and aging effects in the crystal reference.

Integer-N Register

The integer part of the N Counter contains the prescaler and A

and B Counters. It is eight bits wide and offers a divide of

2 + 3P + 3 to 255.

The combination of the integer (255) and the fractional (31767/

31768) gives a maximum N Divider of 256. The minimum

usable PFD is

Maximum

quired Output Frequency

255

()

For use in the European 868 MHz to 870 MHz band, there is a

restriction to using a minimum PFD of 3.4 MHz to allow the

user to have a center frequency of 870 MHz.

PFD Frequency

The PFD frequency is the number of times a comparison is

made between the reference frequency and the feedback signal

from the output.

The higher the PFD frequency, the more often a comparison is

made at the PFD. This means that the frequency lock time will

be reduced when jumping from one frequency to another by

increasing the PFD. Having a PFD of > 5 MHz will reduce the

available output power due to EN300-220 spurious regulations.

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