SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

March 4, 2000

Version 1.0

5

VSYNC

PCLK

Y[7:0]/UV[7:0]

HREF

Horizontal Timing

VSYNC

Even Field 1 (FODD=0)

Odd Field 1 (FODD=1)

t8

t8

t6

t7

t5

t4

t2

t1

t3

2

1

352

351

Valid Data

T

VS

T

LINE

T

VE

1 Line

Y[7:0]/UV[7:0]

Vertical Timing

Figure 3. Zoom Video Port Timing

Notes:

1.

Zoom Video Port format output signal includes:

VSYNC: Vertical sync pulse.

HREF: Horizontal valid data output window.

PCLK: Pixel clock used to clock valid data and CHSYNC into Zoom V Port. Default frequency is 8.86MHz when use

17.73MHz as system clock. Rising edge of PCLK is used to clock the 16 Bit data.

Y[7:0]: 8 Bit luminance data bus.

UV[7:0]: 8 Bit chrominance data bus.

2.

All timing parameters are provided in Table 13. Zoom Video Port AC Parameters.

1.2.5

QCIF Format

A QCIF mode is available for applications where higher resolution

image capture is not required. Only half of the pixel rate is required

when programmed in this mode. Default resolution is 176 x 144

pixels and can be programmed for other resolutions. Refer to Table 7.

QCIF Digital Output Format (YUV beginning of line) and Table 8.

QCIF Digital Output Format (RGB raw data beginning of line) for

further information.

1.2.6

Video Output

The video output port of the OV6630/OV6130 image sensors

provides a number of output format/standard options to suit many

different application requirements. Table 2. Digital Output Format,

below, indicates the output formats available. These formats are user

programmable through the I

Format).