MP2325

– 24V, 3A SYNC STEP DOWN CONVERTER

MP2325 Rev. 1.0

www.MonolithicPower.com

13

12/4/2013

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Selecting the Output Capacitor

The output capacitor (C2)

is required to

maintain the DC output voltage. Ceramic,

tantalum, or low ESR electrolytic capacitors are

recommended.

Low

ESR

capacitors

are

preferred to keep the output voltage ripple low.

The output voltage ripple can be estimated by:

OUT

OUT

OUT

ESR

S

1

IN

S

VV

1

V

1

R

f

L

V

8 f

C2









 











 

 

equivalent series resistance (ESR) value of the

output capacitor.

In

the

case

of

ceramic

capacitors,

the

impedance

at

the

switching

frequency

is

dominated by the capacitance. The output

voltage

ripple

is

mainly

caused

by

the

capacitance.

For

simplification,

the

output

voltage ripple can be estimated by:

OUT

OUT

OUT

2

IN

S1

VV

ΔV

1

V

8 f

L

C2





 





 



In the case of tantalum or electrolytic capacitors,

the ESR dominates the impedance at the

switching frequency. For simplification, the

output ripple can be approximated to:

OUT

OUT

OUT

ESR

IN

S1

VV

ΔV

1

R

f

L

V





 









The characteristics of the output capacitor also

affect the stability of the regulation system. The

MP2325 can be optimized for a wide range of

capacitance and ESR values.

External Bootstrap Diode

An external bootstrap diode may enhance the

efficiency

of

the

regulator,

the

applicable

conditions of external BST diode are:

IN

OUT

V

V

>65%

In these cases, an external BST diode is

recommended from the VCC pin to BST pin, as

shown in Figure 6.

MP2325

Figure 6: Add Optional External

Bootstrap Diode to Enhance Efficiency

The recommended external BST diode is

IN4148, and the BST cap is 0.1

μF─1μF.

PC Board Layout

(6)

PCB layout is very important to achieve stable

operation. Please follow these guidelines and

take Figure 7 as reference.

1) Keep the connection of input ground and

GND pin as short and wide as possible.

2) Keep the connection of input capacitor and

IN pin as short and wide as possible.

3) Ensure all feedback connections are short

and direct. Place the feedback resistors and

compensation components as close to the chip

as possible.

4) Route SW away from sensitive analog areas

such as FB.

Notes:

6) The recommended layout is based on the Figure 8 Typical

Application circuit on the next page.