MP2454―36V, 0.6A, STEP-DOWN CONVERTER

MP2454 Rev. 1.01

www.MonolithicPower.com

12

9/18/2015

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2015 MPS. All Rights Reserved.

capacitor, add external circuitry to ensure that the

bootstrap voltage is in the normal operation

region.

Low Dropout Operation (LDO)

The MP2454 is designed to operate at a 100%

duty cycle as long as the voltage difference

across BST to SW is greater than 2.5V; this

improves dropout. When the voltage from BST to

SW drops below 2.5V, an under-voltage lockout

(UVLO) circuit turns off the high-side MOSFET

(HS-FET), and an internal low-current switch

pulls the SW node low to refresh the charge on

the BST capacitor. After the BST capacitor

voltage is re-charged, the HS-FET turns on again

to regulate the output. Since the supply current

sourced from the BST capacitor is low, the HS-

FET can remain on for more switching cycles

than are required to refresh the capacitor, thus

increasing the effective duty cycle of the

switching regulator. The low-dropout operation

makes the MP2454 suitable for the automotive

cold crank.

The voltage drop across the power MOSFET, the

inductor resistance, the low-side diode, and the

printed circuit board resistance influence heavily

the effective duty cycle during regulator dropout.

Enable Control and Frequency

Synchronization

EN/SYNC is a digital control pin that turns the

regulator on and off. When EN is pulled below 1V

for longer than 2µs, the chip enters the lowest

shutdown current mode. Forcing EN/SYNC

above 1.8V for longer than 200ns turns on the

device. Internally, a 1.2MΩ resistor is connected

from EN to GND. So when left floating, the

device pulls EN down to GND, and the chip is

disabled.

A Zener diode is connected from EN to GND

internally. The typical clamping voltage of the

Zener diode is 7.5V, so VIN can be connected to

EN through a high value resistor if the system

does not have another logic input acting as an

enable signal. The resistor needs to be designed

to limit the EN sink current to less than 150μA.

An external clock with a frequency range of

350kHz to 2.3MHz can be used to synchronize

the device through EN/SYNC. The internal

clock’s rising edge is synchronized to the

external clock’s rising edge.

If a clock on period exceeds 4µs or an off period

exceeds 2µs, the device interprets the signal as

an enable input and disables synchronization.

Frequency Programmable

sets the MP2454’s oscillating frequency. For

additional details on the relationship between

section.

The oscillating frequency is related to the FB

voltage. When the FB voltage decreases, the

oscillating frequency decreases accordingly and

becomes one fifth of the nominal value (when FB

is 0). This frequency foldback scheme prevents

inductor current runaway during start-up or an

output short circuit.

Under-Voltage Lockout (UVLO)

VIN UVLO protects the chip from operating at an

insufficient supply voltage. The UVLO rising

threshold is 2.9V while its falling threshold is

2.65V.

Soft Start (SS)

Soft start (SS) prevents the converter output

voltage from overshooting during start-up. When

the soft-start period begins, an internal current

source charges the external soft-start capacitor.

When the SS voltage falls below the internal

reference (REF), the SS overrides REF as the

error amplifier reference. When SS exceeds REF,

REF acts as the reference.

The SS time is calculated with Equation (1):

(V)

V

A)

(

I

(ms)

t

(nF)

C

REF

SS

SS

SS







(1)

0.8V reference voltage. It can be used for

tracking and sequencing.

Thermal Shutdown (TSD)

Thermal shutdown prevents the chip from

thermal runaway. When the die temperature