MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER

MP8867 Rev.1.01

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18

2/21/2017

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consisting of a data line (SDA) and a clock line

(SCL). The lines are pulled externally to a bus

voltage when they are “idle.” A master device

connects to the line, generates the SCL signal

and

device

address,

and

arranges

the

communication

sequence.

The

MP8867

flexibility to the power supply solution. The

output voltage, transition slew rate, or other

interesting

parameters

can

be

controlled

“1100010” (BINARY), and “6A” (HEX) or

“1101010” (BINARY) if A0 is pulled to ground.

Data Validity

One clock pulse is generated for each data bit

transferred. The data on the SDA line must be

stable during the high period of the clock. The

high or low state of the data line can only

change when the clock signal on the SCL line is

low (see Figure 6).

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Figure 6: Bit Transfer on the I

Start and stop are signaled by the master

device, which signifies the beginning and the

defined as the SDA signal transitioning from

high to low while the SCL is high. The stop

condition is defined as the SDA signal

transitioning from low to high while the SCL is

high (see Figure 7).

SDA

SCL

P

STOP condition

SDA

SCL

S

START condition

Figure 7: Start and Stop Conditions

Start and stop conditions are always generated

by the master. The bus is considered busy after

the start condition. The bus is considered free

again after a minimum of 4.7µs after the stop

condition. The bus stays busy if a repeated start

(Sr) is generated instead of a stop condition.

The start (S) and repeated start (Sr) conditions

are functionally identical.

Transfer Data

Every byte put on the SDA line must be 8 bits

long. Each byte has to be followed by an

acknowledge bit. The acknowledge-related

clock pulse is generated by the master. The

transmitter releases the SDA line (high) during

the acknowledge clock pulse. The receiver

must pull down the SDA line during the

acknowledge clock pulse, so that it remains at a

stable low during the high period of this clock

pulse.

Data transfers follow the format shown in Figure

8. A slave address is sent after the start

condition (S). This address is 7 bits long,

followed by an eighth bit, which is a data

direction bit (R/W). A zero indicates a

transmission (write), and a one indicates a

request for data (read). A data transfer is

always terminated by a stop condition (P)

generated by a master. However, if a master

still wishes to communicate on the bus, it can

generate a repeated start condition (Sr) and

address another slave without first generating a

stop condition.

S

1 7

8

9

1 7

8

9

1 7

8

9

P

STOP

condition

START

condition

DATA

ACK

DATA

ACK

ADDRESS

ACK

R/W

SDA

SCL

Figure 8: A Complete Data Transfer

The MP8867 requires a start condition, a valid

byte for a single data update. The MP8867

acknowledges the receipt of each byte by

pulling the SDA line low during the high period

selects the MP8867, which performs an update

on the falling edge of the LSB.