MP3910 –PEAK CURRENT MODE BOOST CONTROLLER

MP3910 Rev. 1.11

www.MonolithicPower.com

19

11/6/2014

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Bottom Layer

Figure 3: Boost PCB Layout

C

9

8

7

6

1

2

3

4

5

10

GND

GND

Vin

CIN

Vout

T1

U1

U2

Q1

Top Layer

Input

GND

Output

GND

Bottom Layer

Figure 4: Fly-back PCB Layout

For flyback topology PCB layout:

1. Keep the input loop as short as possible

between input cap, transformer, MOSFET,

current sense resistor and GND plane for

minimal noise and ringing.

2. Keep the output loop between rectifier diode,

output cap and transformer as short as

possible.

and transformer should be as small as

possible

4. The VCC capacitor must be placed close to

the VCC pin for best decoupling.

5. The feedback trace should be far away from

noise source such as drain of power FET.

6. Use single point connection between power

GND and signal GND.

Refer to figure 4 for flyback layout, which is

referenced to schematic on page 1. For more

detail

information,

refer

to

flyback

EVB

datasheet.

Design Example

Below is a design example following the

application guidelines for the specifications:

Table 1: Boost Design Example

10-20V

24V

300kHz

The detailed application schematic is shown in

Figure 8. And there is another design example

for fly-back application in Figure 6.

Table 2: Fly-back Design Example

36-72V

12V

250kHz

The typical performance and circuit waveforms

of flyback have been shown in the Typical

Performance Characteristics section. For more

device applications, please refer to the related

Evaluation Board Datasheets.