MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE

MP2930 Rev. 1.01

www.MonolithicPower.com

14

10/30/2013

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be calculated based on Equations (13) and (14):

(us)

6.25

SS

R

1.1

d2

t

25

3

2









(13)





(us)

6.25

SS

R

1.1

VID

V

d4

t

25

3

2











(14)

For example, when ID is set to 1.5V and the

After the DAC voltage reaches the final ID

setting, VR_RDY will be set to high with the

Fault Monitoring and Protection

The MP2930 actively monitors output voltage

and current to detect fault conditions. One

common power good indicator is provided for

linking

to

external

system

monitors.

The

schematic in Figure 8 outlines the interaction

between the fault monitors and the VR_RDY

signal.

VR_RDY Signal

The VR_RDY pin is an open-drain logic output

to

indicate

that

the soft-start

period

has

completed and the output voltage is within the

regulated range. VR_RDY is pulled low during

shutdown and releases high after a successful

pulled low when an under-voltage or over-

voltage condition is detected, or the controller is

disabled by a reset from EN_PWR, EN_VTT,

POR, or ID OFF-code.

Under-voltage Detection

The undervoltage threshold is set at 50% of the

ID code. When the output voltage at VSEN is

below the undervoltage threshold, VR_RDY is

pulled low.

Over-voltage Protection

Regardless of the VR being enabled or not, the

MP2930 over-voltage protection (OVP) circuit

will be active after its POR. The OVP thresholds

are different at different operation conditions.

When VR is not enabled and during the soft-

is 1.275V. Once the controller detects valid ID

input, the OVP trip point will be changed to

DAC + 175mV.

Two actions are taken by the MP2930 to protect

the microprocessor load when an over-voltage

condition occurs.

SOFT-START, FAULT

AND CONTROL LOGIC

50%

DAC

VDIFF

VID + 0.175V

85uA

I

VR_RDY

OC

UV

OV

AVG

Figure 8

—VR_RDY and Protection Circuitry

At the beginning of an over-voltage event, all

PWM outputs are commanded low instantly

(>20ns). This causes the MP86961 to turn on

the lower MOSFETs and pull the output voltage

below a level to avoid damaging the load. When

the VDIFF voltage falls below the DAC + 75mV,

PWM signals enter a high-impedance state,

and the SD pin is pulled low to turn off the

MP86961.

Once an over-voltage condition is detected,

normal

PWM

operation

ceases

until

the

MP2930 is reset. Cycling the voltage on

EN_PWR, EN_VTT or VCC below the POR-

falling threshold will reset the controller. Cycling

the ID codes will not reset the controller.

Over-current Protection

MP2930

has

two

levels

of

over-current

protection. Each phase is protected from a

sustained over-current condition by limiting its

peak

current,

while

the

combined

phase

currents are protected on an instantaneous

basis.

In instantaneous protection mode, the MP2930

detect an over-current condition. The average

current is continually compared with a constant

85µA reference current, as shown in Figure 8.