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dc1908af

DEMO MANUAL DC1908A

DC1908A SETUP

DC Power

The DC1908A requires ±16VDC and draws approximately

100mA from the positive supply. Most of this supply cur-

rent is consumed by the CPLD, op amps, regulators and

discrete logic on the board. The +16VDC input voltage

powers the ADC through LT1763 regulators which pro-

vide protection against accidental reverse bias. Additional

regulators provide power for the CPLD and op amps. See

Figure 1 for connection details.

Clock Source

to CLK IN. The clock input is AC coupled so the DC level

of the clock signal is not important. A clock source like

the Rohde & Schwarz SMB100A is recommended. Even

a good generator can start to produce noticeable jitter at

low frequencies. Therefore it is recommended for lower

sample rates to divide down a higher frequency clock to

the desired sample rate. The ratio of clock frequency to

conversion rate is 62:1 for 18-bit parts and 50:1 for 16-

bit parts. If the clock input is to be driven with logic, it is

recommended that the 50Ω terminator (R5) be removed.

Slow rising edges may compromise the SNR of the con-

verter in the presence of high amplitude higher frequency

input signals.

Analog Input

The default setup for the DC1908A requires that only AIN+

is driven. Versions A, B and C of the DC1908A convert the

single-ended signal at AIN+ to a fully-differential signal

that is then fed to the ADC as shown in Figure 2. Single-

ended versions D, E, F, G, H and I simply buffer the signal

applied at AIN+ and feed it to the ADC as shown in Figure 3.

To bypass the single-ended-to-differential converter or

buffer, disable amplifier U10 by moving R32 and R35 to

R31 and R38 respectively. Disabling U10 will require that

both AIN+ and AIN– be driven with a low output imped-

ance signal source.

Data Output

Parallel data output from this board (0V to 3.3V default),

if not connected to the DC718, can be acquired by a logic

analyzer, and subsequently imported into a spreadsheet,

or mathematical package depending on what form of

digital signal processing is desired. Alternatively, the

data can be fed directly into an application circuit. Use

CLKOUT (Pin 3) of P1 to latch the data. The data can be

latched using either edge of this signal. The data output

signal levels at P1 can also be reduced to 0V to 2.5V if

the application circuit cannot tolerate the higher voltage.

This is accomplished by moving the VCCIO jumper (JP3)

to the 2.5V position.

Reference

The default reference is the LTC2338-18 4.096V internal

reference. The LTC6655 5V external reference can be used

by adding R37 and moving the REF jumper (JP2) to the

EXT position. This will increase the input range at AIN+

and AIN– to ±12.5V. Also, an external reference can be

used by removing R37 and applying a reference voltage

to the VREF (E3) terminal with the REF jumper in the EXT

position. If an external reference is used it must settle

quickly in the presence of glitches on the REF pin. The

Figure 2. Single-Ended to Differential Converter

Figure 3. Single-Ended Buffer