Electronic Components Datasheet Search
  English  ▼

X  

MP5014A Datasheet(PDF) 11 Page - Monolithic Power Systems

Part # MP5014A
Description  12 V, 5 A, Programmable Current-Limit Switch with Over-Volatge Clamp and Slew-Rate Control in TSOT23-8
PDF  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP5014A Datasheet(HTML) 11 Page - Monolithic Power Systems

Back Button MP5014A Datasheet HTML 6Page - Monolithic Power Systems MP5014A Datasheet HTML 7Page - Monolithic Power Systems MP5014A Datasheet HTML 8Page - Monolithic Power Systems MP5014A Datasheet HTML 9Page - Monolithic Power Systems MP5014A Datasheet HTML 10Page - Monolithic Power Systems MP5014A Datasheet HTML 11Page - Monolithic Power Systems MP5014A Datasheet HTML 12Page - Monolithic Power Systems MP5014A Datasheet HTML 13Page - Monolithic Power Systems MP5014A Datasheet HTML 14Page - Monolithic Power Systems  
Zoom Inzoom in Zoom Outzoom out
 11 / 14 page
background image
MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH
MP5014A Rev. 1.0
www.MonolithicPower.com
11
6/23/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
APPLICATION INFORMATION
Current Limit
The desired current limit is a function of the
external current limit resistor (see Table 2).
Table 2—Current limit vs. current limit resistor
(VCC= 12 V)
RLIMIT (Ω)
15.4
22
24.9
30
49.9
100
Trip
current (A)
7.95
5.62
5.23
4.57
3.43
2.64
Hold
current (A)
5.61
3.81
3.35
2.78
1.69
0.88
Rise Time
The rise time is a function of the capacitor (CDV/DT)
on DV/DT (see Table 3).
Table 3—Rise time vs. CDV/DT
CDV/DT
none
33 pF
470 pF
1 nF
Rise time
(typically, ms)
1
1.45
9.6
20.3
* NOTE: Rise Time = K
RT*(50 Pf + Cdv/dt), KRT = 18.1E6
The rise time is measured from 10 percent to 90
percent of the output voltage (see Figure 2).
Figure 2—Rise time
PCB LAYOUT GUIDELINES
Efficient PCB layout is critical to achieve stable
operation. Please refer to Figure 3 and follow the
guidelines below:
1. Place RLIMIT close to I-LIMIT.
2. Place CDV/DT close to DV/DT and the input
capacitor close to VCC.
3. Ensure there is a large enough copper
area near VCC and source to achieve
better thermal performance.
Top Layer
Bottom Layer
Figure 3―Recommended PCB layout



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com