LTC3124 datasheet(8/28 Pages) LINER

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LTC3124

3124f

For more information www.linear.com/LTC3124

PIN FUNCTIONS

device. Place a low ESR ceramic bypass capacitor of at

least 10µF from VIN to PGND. X5R and X7R dielectrics

are preferred for their superior voltage and temperature

characteristics.

PWM/SYNC (Pin 6): Burst Mode Operation Select and

Oscillator Synchronization.

Do not leave this pin floating.

• PWM/SYNC = High. Disable Burst Mode operation and

maintain low noise, constant frequency operation.

• PWM/SYNC = Low. The converter operates in Burst

Mode, independent of load current.

• PWM/SYNC = External CLK. The internal oscillator is

synchronized to the external CLK signal. Burst Mode

operation is disabled. A clock pulse width of 100ns

minimum is required to synchronize the oscillator.

An external resistor MUST BE connected between RT

and SGND to program the oscillator slightly below the

desired synchronization frequency.

In non-synchronized applications, repeated clocking of

the PWM/SYNC pin to affect an operating mode change

is supported with these restrictions:

• Boost Mode (VOUT > VIN): IOUT < 3mA: fPWM/SYNC ≤

10Hz, IOUT ≥ 3mA: fPWM/SYNC ≤ 5kHz.

• Buck Mode (VOUT < VIN): IOUT < 5mA: fPWM/SYNC ≤

2.5Hz, IOUT ≥ 5mA: fPWM/SYNC ≤ 5kHz.

VCC (Pin 7): VCC Regulator Output. Connect a low ESR

filter capacitor of at least 4.7µF from this pin to SGND to

provide a regulated rail approximately equal to the lower of

VIN and 4.25V. When VOUT is higher than VIN, and VIN falls

below 3V, VCC will regulate to the lower of approximately

VOUT and 4.25V. A UVLO event occurs if VCC drops below

1.5V, typical. Switching is inhibited, and a soft-start is

initiated when VCC returns above 1.6V, typical.

RT (Pin 8): Frequency Adjust Pin. Connect to SGND

through an external resistor (RT) to program the oscillator

frequency according to the formula:

fOSC ≅

fSWITCH =

fOSC

≅

where fOSC is in MHz and RT is in kΩ.

VC (Pin 9): Error Amplifier Output. A frequency com-

pensation network is connected from this pin to SGND

to compensate the control loop. See Compensating the

Feedback Loop section for guidelines.

FB (Pin 10): Feedback Input to the Error Amplifier. Con-

nect the resistor divider tap to this pin. Connect the top

of the divider to VOUT and the bottom of the divider to

SGND. The output voltage can be adjusted from 2.5V to

15V according to the formula:

VOUT =1.2V • 1+









SD(Pin11):LogicControlledShutdownInput.Pullingthis

pin above 1.6V enables normal, free-running operation.

Forcing this pin below 0.25V shuts the LTC3124 off, with

quiescentcurrentbelow1µA.

Donotleavethispinfloating.

SGND (Pin 12): Signal Ground. When laying out your PC

board, provide a short, direct path between SGND and the

groundreferencedsidesofalltheappropriatecomponents

connecting to pins RT, VC, and FB.

VOUTA,VOUTB(Pin13,Pin15):OutputVoltageSensesand

theSourceoftheInternalSynchronousRectifierMOSFETs.

Driver bias is derived from VOUT. Connect the output filter

capacitor from VOUT to PGND, close to the IC. A minimum

value of 10µF ceramic per phase is recommended. VOUT is

disconnected from VIN when SD is low. VOUTA and VOUTB

must be tied together.

NC(Pin14):NoConnect.Notconnectedinternally.Connect

this pin to VOUTA/VOUTB to provide a wider VOUT copper

plane on the printed circuit board.

CAP (Pin 16): Serves as the Low Reference for the Syn-

chronous Rectifiers Gate Drives. Connect a low ESR filter

capacitor (typically 100nF) from this pin to VOUTtoprovide

an elevated ground rail, approximately 5.4V below VOUT,

used to drive the synchronous rectifiers.

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