73M2921

Advanced Single

Chip Modem

February 99 Rev M

TDK Semiconductor

Page 7 of 41

POWER CONTROL TIMING

DESCRIPTION

MIN

TYP

MAX

UNIT

Powerup input to active state

250

µs

Powerup input to inactive state

50

µs

Table 5 - Power Control Timing

DCE-DTE INTERFACE

The 73M2921 is designed to interface with a synchronous port such as that found on the TDK 73M2910. It also

provides a parallel control interface. This parallel interface appears as an 8 bit memory mapped peripheral to the

host controller.

SERIAL DATA INTERFACE

The serial data interface is a four pin bi-directional port. It consists of the TXD and RXD data paths (LSBit

shifted in and out first, respectively), the TXCLK and RXCLK serial clock outputs associated with the data pins.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

TXDS

DATA to TXCLK

Tbd

ns

TXDH

TXCLK to Data Hold

Tbd

ns

TRD

RXCLK to RXD Delay

Tbd

ns

Table 3 - Serial Data Interface Timing

Synchronous Mode

FIGURE 7 - Serial Data Interface Timing Diagram

MICROCONTROLLER TO 73M2921 PARALLEL INTERFACE

The interface between the microcontroller (

µC) and the 73M2921 is accomplished through the 2 bit address

UA[1:0] and 8 bit data bus UD[7:0],

5', :5, and &6. The 73M2921 chip provides an interrupt output to the µC

(

8,17). The 73M2921 and the µC communicate through two 16 bit registers, CR0 and the Mailbox; all µC

accesses are 8 bit transfers. All reading and writing functions to and from the 73M2921 internal registers as well

TXD, RXD

TXCLK or

RXCLK

t

XDS

t

XDS

t

XDH

t

RD

Sample Time