73M2921

Advanced Single

Chip Modem

February 99 Rev M

TDK Semiconductor

Page 13 of 41

REGISTER NAME:

CR1 Configuration Register 1

ADDRESS: 05H (101b)

CR1 controls Diagnostic modes, data wait, 5V power supply detect, speaker volume, ADC/DAC sampling rate,

slave sync, digital loopback, digital interface loopback, enable digital interface, and enable timer. It also has bits

that are reserved for test modes.

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EN

TIMER

TEST

3

TEST

2

EN

DIGI

TDK

TDK

0

0

SLAVE

SYNC

16

KHZ

SPKR VOL

(1:0)

05V

DETECT

DATA

WAIT

DIAG

MODE

BIT NO.

NAME

CONDITION

DESCRIPTION

D0

Diagnostic

Mode

(Test Mode)

Always 0

DIAGNOSTIC MODE: Must be zero.

D1

Data Wait

(Test Mode)

Always 0

Must be zero.

D2

5V Detect

(output)

This is a logical 1 if the power supply to the 73M2921 is in the

5V range.

Note, this signal is valid only when EN ANALOG

(CR2: D10) is enabled.

D3

0

Not Used.

D4,D5

Speaker

Volume (1:0)

2

1

1

1

0

0

1

00

High Volume

Medium Volume

Low Volume

Speaker off

1

The ADC/DAC sampling rates are 16.0KHz

D6

16KHz

0

The ADC/DAC sampling rates are 14.4KHZ (Default)

1

The phase error register measures the time between the rising

edge of RXC and the rising edge of TXC

D7

Slave Sync

(modem test

mode)

0

The phase error register measures the time between the rising

edge of EXC and the rising edge of TXC

D8,D9

0

Not Used

D10

TDK

Always 0

TDK proprietary.

D11

TDK

Always 0

TDK proprietary.

1

Enables the digital serial interface. Pins TXCLK, RXCLK, TXD,

and RXD are enabled. Must be set to one for normal operation.

D12

Enable Digital

Interface

0

Tri-states pins TXCLK and RXCLK (with a weak pull-down to 0).

RXD pin is driven to a 1, TXD is disabled at the input pin, and

the timer baud clocks are forced low.

D13

Test 2

0

Must be zero.

D14

Test 3

0

Must be zero.

D15

Enable Timer

1

When set to 1, sample, bit, and clocks for transmit and receive

are running. Baud (provided that EN DIGI is true).



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