LTC3607 datasheet(6/20 Pages) LINER

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LTC3607

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pin FuncTions

PVIN1, PVIN2, SVIN (Pins 6, 7, 3/Pins 4, 5, 1): Main Power

Supply. Must be closely decoupled to GND. These inputs

may each be powered from different supply voltages.

Connect SVIN to either PVIN1 or PVIN2, whichever one

is higher. For applications where it’s not known which

PVIN(1or2)ishigher,connectexternaldiodesbetweenSVIN

to both PVIN1 and PVIN2 to ensure that SVIN is less than a

diode drop from the higher of PVIN1 or PVIN2.

PGND1,PGND2,SGND,PGND(Pins4,9,10,12,Exposed

Pad Pin 17/Pins 2, 7, 8, 10, Exposed Pad Pin 17): Main

Ground. Connect to the (–) terminals of COUT1, COUT2, and

CIN. The exposed pad must be soldered to PCB ground for

electricalcontactandratedthermalperformance.AllSGND

and PGND pins must be externally connected to ground.

VFB1 (Pin 15/Pin 13): Regulator 1 Output Feedback.

Receives the feedback voltage from the external resistor

divider across the regulator 1 output. Nominal voltage for

this pin is 0.6V.

SW1 (Pin 5/Pin 3): Regulator 1 Switch Node Connection

to the Inductor. This pin switches from PVIN1 to PGND1.

RUN1 (Pin 16/Pin 14): Regulator 1 Enable. Forcing this

pin high (above 3V) enables regulator 1, while forcing it

to SGND causes regulator 1 to shut down. It is possible

to use a 3.3V source to drive this pin, or tie it to SVIN.

An internal soft-start limits the rise time to a minimum

of 0.35ms.

PGOOD1 (Pin 2/Pin 16): Regulator 1 Power Good. This

common-drain logic output is pulled to SGND when the

channel 1 output voltage is not within ±8.5% of regulation.

VFB2 (Pin 14/Pin 12): Regulator 2 Output Feedback.

Receives the feedback voltage from the external resistor

divider across the regulator 2 output. Nominal voltage for

this pin is 0.6V.

SW2 (Pin 8/Pin 6): Regulator 2 Switch Node Connection

to the Inductor. This pin switches from PVIN2 to PGND2.

RUN2 (Pin 13/Pin 11): Regulator 2 Enable. Forcing this

pin high (above 3.0V) enables regulator 2, while forcing

it to SGND causes regulator 2 to shut down. It is possible

to use a 3.3V source to drive this pin, or tie it to SVIN.

An internal soft-start limits the rise time to a minimum

of 0.35ms.

PGOOD2 (Pin 11/Pin 9): Regulator 2 Power Good. This

common-drain logic output is pulled to SGND when the

channel 2 output voltage is not within ±8.5% of regulation.

MODE/SYNC (Pin 1/Pin 15): Combination Mode Selec-

tion and Oscillator Synchronization. This pin controls the

light-load behavior of the device. Forcing this pin to SGND

selects pulse-skipping mode. Floating this pin or forcing

it above 1V selects Burst Mode operation. The internal

oscillation frequency can be synchronized to an external

oscillator applied to this pin and pulse-skipping mode is

automatically selected.

(QFN/MSE)

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