March 2003

11

MICRF500

MICRF500

Micrel

The component values will be:

C116

22n

R109

10k

C101

100p

OUT

R101

33k

IN

C115

1n

Figure 5. Third Order Loop Filter

With this loop filter, internal modulation up to 2400bps is

possible. The PLL lock time from power-down to Rx will be

approximately 1ms.

Modulation Outside PLL (Closed Loop)

When modulation is applied outside the PLL, it means that the

PLL should not track the changes in the loop due to the

modulation signal. A loop filter with relatively low bandwidth

is therefore necessary. The exact bandwidth will depend on

the actual modulation rate. Because the loop bandwidth will

be significantly lower than the comparison frequency, a

second order loop filter will normally give adequate attenua-

tion of the comparison frequency. If not, a third order loop filter

may give the extra attenuation needed.

Example 2:

Radio frequency

f

RF

868MHz

Comparison frequency

f

C

140kHz

Loop bandwidth

BW

900Hz

VCO gain

K

o

30MHz/V

Phase comparator gain

K

d

125

µA/rad

Phase margin

j

61

°

The component values will be:

C16

68n

R9

10k

R10

10k

OUT

IN

C15

4.7n

CmpR

Figure 6. Second Order Loop Filter

Data rates above approximately 19200baud (including

Manchester coding) can be used with this loop filter without

significant tracking of the modulating signal. PLL lock time will

be approximately 4ms.

If a faster PLL lock time is wanted, the charge pump can be

made to deliver a current of 500

µA per unit phase error, while

an open drain NMOS on chip (Pin 10, CmpR) switches in a

second damping resistor (R10) to ground as shown in Figure

6. Once locked on the correct frequency, the PLL automati-

cally returns to standard low noise operation (charge pump

current: 125

µA/rad). If correct settings have been made in the

control word (cpmp1 = 1, cpmp0 = 0), the fast locking feature

is activated and will reduce PLL lock time by a factor of two

without affecting the phase margin in the loop.

Components C17, C18 C19, R11, R12 and R13 (see applica-

tion circuit) are necessary if FSK modulation is applied to the

VCO. Data entered at the DATAIXO pin will then be fed

through the Mod pin (Pin 11) which is a current output. The pin

sources a current of 50

µA when Logic 1 is entered at the

DATAIXO and drains the current for Logic 0. The capacitance

of C17 will set the order of filtering of the baseband signal. A

large capacitance will give a slow ramp-up and therefore a

high order of filtering of the baseband signal, while a small

capacitance gives a fast ramp-up, which in turn also gives a

broader frequency spectrum. Resistors R11 and R12 set the

frequency deviation. If C18 is large compared to C17, the

frequency deviation will be large. R13 should be large to

avoid influencing the loop filter. Pin DATAIXO must be kept

in tri-state from the time Tx-mode is entered until one starts

sending data.

Modulation Outside PLL, Dual-Loop Filters

Modulation outside the PLL requires a loop filter with a

relatively low bandwidth compared to the modulation rate.

This results in a relatively long loop lock time. In applications

where modulation is applied to the VCO, but at the same time

a short start-up time from power down to receive mode is

needed, dual-loop filters can be implemented. Figure 7

shows how to implement dual-loop filters.

R109

10k

R102 33k

R8 89k

R9

10k

R10

10k

Pin4

Pin10

Pin9

towards_VCO

CMPOUT

DFC

C16

68n

C15

4.7n

C116

1n

C115

22n

C103

100p

FLC

Figure 7. Dual-Loop Filters

The loop filter used in transmit mode is made up of C15, C16,

R9 and R10. The fast lock feature is also included (internal

NMOS controlled by FLC, Fast Lock Control). This filter is

automatically switched in/out by an internal NMOS at Pin 4,

QchOut, which is controlled by DFC (Dual Filter Control). Bits

OutS2, OutS1, OutS0 must be set to 110. When QchOut is

used to switch the Tx loop filter to ground, neither QchOut nor

IchOut can be used as test pins to look at the different receiver

signals. The receive mode loop filter comprises C115, C116,

R109, R101 and C101.

Modulation Outside PLL (Open Loop)

In this mode the charge pump output is tri-stated. The loop is

open and will therefore not track the modulation. This means

that the loop filter can have a relatively high bandwidth, which

give short switching times. However, the loop voltage will

decrease with time due to current leakage. The transmit time

will therefore be limited and is dependent on the bandwidth of

the loop filter. High bandwidth gives low capacitor values and

the loop voltage will decrease faster, which gives a shorter

transmit time.

The loop is closed until the PLL is locked on the desired

frequency and the power amplifier is turned on. The loop

immediately opens when the modulation starts. The loop will

not track the modulation, but the modulation still needs to be

DC free due to the AC coupling in the modulation network.