March 2003

15

MICRF500

MICRF500

Micrel

Name

Description

A1

frequency divider A1, 6 bits

A0

frequency divider A0, 6 bits

N1

frequency divider N1, 12 bits

N0

frequency divider N0, 12 bits

M1

frequency divider M1, 10 bits

M0

frequency divider M0, 10 bits

RxFilt

1=external capacitor for filtering of Rx data signal

Pa2

gain setting in power amplifier

Pa1

pa2, pa1, pa0 = 0 : lowest output power

Pa0

pa2, pa1, pa0 = 1 : highest output power

Gc

gain control in power amplifier buffer: 1=high gain

gain control in preamplifier in receiver: 1=high gain

ByLNA

1 = the LNA is bypassed

Ref6

Ref5

reference settings in lock detector

Ref4

Ref3

all 0’s: highest reference

Ref2

all 1’s: lowest reference

Ref1

Ref0

Cpmp1

charge pump setting:

Cpmp1=0, Cpmp0=0 :

±125µA

Cpmp0

Cpmp1=0, Cpmp0=1 :

±500µA

Cpmp1=1, Cpmp0=0 : controlled by LockDet (LD) LD=0:

±500µA, LD=1: ±125µA

Cpmp1=1, Cpmp0=1 : same as previous in Tx. In Rx the current is

±500µA.

Fc1

Active RC-filter settings

Fc1=0, Fc0=0 : 10kHz

Fc1=1, Fc0=0 : 60kHz

Fc0

Fc1=0, Fc0=1 : 30kHz

Fc1=1, Fc0=1 : 200kHz

OutS2

I- and Q-channel

OutS2 OutS1

OutS0 IchOut

QchOut

OutS2

OutS1

OutS0

IchOut

QchOut

OutS1

output select

0

0

0

high Z

high Z

1

0

0

lim_qch

gm_qch

OutS0

0

0

1

sk_ich

sk_qch

1

0

1

gm_ich

lim_ich

0

1

0

gm_ich

gm_qch

1

1

0

high Z

Dual LF

0

1

1

lim_ich

lim_qch

1

1

1

N_div

M_div

sk:_*:Sallen-Key filter output, gm_*:gyrator filter output, lim_*:limiter output, *_div:frequency divider output

(for testing). 110 is for dual-loop filter applications, see “Modulation Outside PLL, Dual-Loop Filters.”

Mod1

Mod1 = 0, Mod0 = 0: FSK modulation can be applied to the VCO

Mod0

Mod1 = 0, Mod0 = 1: FSK modulation can be applied to the VCO: open loop modulation

Mod1 = 1, Mod0 = 0: FSK modulation by switching between the two sets of dividers

Mod1 = 1, Mod0 = 1: FSK modulation by adding/subtracting 1 to divider A1:

f

RT

0 = receive mode 1 = transmit mode

Pu

1 = power up, 0 = power down (When Pu=1, power down is controlled by PuExt)

Table 2. Bit Description