K64F datasheet(63/85 Pages) NXP

63 / 85 page

S15

S13

S15

S17

S18

S15

S16

S14

S16

S11

S12

I2S_BCLK (input)

I2S_FS (output)

I2S_FS (input)

I2S_TXD

I2S_RXD

S19

Figure 32. I2S timing — slave modes

3.8.11.1 Normal Run, Wait and Stop mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in Normal Run, Wait and Stop modes.

Table 53. I2S/SAI master mode timing

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

3.6

I2S_MCLK cycle time

—

I2S_MCLK (as an input) pulse width high/low

45%

55%

MCLK period

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

—

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

45%

55%

BCLK period

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

—

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

-1

—

I2S_TX_BCLK to I2S_TXD valid

—

I2S_TX_BCLK to I2S_TXD invalid

—

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

22.5

—

S10

I2S_RXD/I2S_RX_FS input hold after

I2S_RX_BCLK

—

Peripheral operating requirements and behaviors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 11/2016

NXP Semiconductors

K64F Datasheet(PDF) 63 Page - NXP Semiconductors

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