LP5018 datasheet(19/49 Pages) TI1

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LP5018, LP5024

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SLVSEB8 – MARCH 2018

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Table 3. Chip Address

SLAVE ADDRESS

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Independent

ADDR1

ADDR0

1 or 0

Broadcast

1 or 0

8.5.1.5 Control-Register Write Cycle

•

The master device generates a start condition.

•

The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).

•

The slave device sends an acknowledge signal if the slave address is correct.

•

The master device sends the control register address (8 bits).

•

The slave device sends an acknowledge signal.

•

The master device sends the data byte to be written to the addressed register.

•

The slave device sends an acknowledge signal.

•

If the master device sends further data bytes, the control register address of the slave is incremented by 1

after the acknowledge signal. To reduce program load time, the device supports address auto incrementation.

The register address is incremented after each 8 data bits.

•

The write cycle ends when the master device creates a stop condition.

Figure 14. Write Cycle

8.5.1.6 Control-Register Read Cycle

•

The master device generates a start condition.

•

The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).

•

The slave device sends an acknowledge signal if the slave address is correct.

•

The master device sends the control register address (8 bits).

•

The slave device sends an acknowledge signal.

•

The master device generates a repeated-start condition.

•

The master device sends the slave address (7 bits) and the data direction bit (R/W = 1).

•

The slave device sends an acknowledge signal if the slave address is correct.

•

The slave device sends the data byte from the addressed register.

•

If the master device sends an acknowledge signal, the control-register address is incremented by 1. The

slave device sends the data byte from the addressed register. To reduce program load time, the device

supports address auto incrementation. The register address is incremented after each 8 data bits.

•

The read cycle ends when the master device does not generate an acknowledge signal after a data byte and

generates a stop condition.

Figure 15. Read Cycle

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