LP5018 datasheet(41/49 Pages) TI1

41 / 49 page

LP5018, LP5024

www.ti.com

SLVSEB8 – MARCH 2018

Product Folder Links: LP5018 LP5024

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11 Layout

11.1 Layout Guidelines

To prevent thermal shutdown, the junction temperature, TJ, must be less than T(TSD). If the voltage drop across

the output channels is high, the device power dissipation can be large. The LP50xx device has very good

thermal performance because of the thermal pad design; however, the PCB layout is also very important to

ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is

essential for the long-term reliability of the device.

Use the following guidelines when designing the device layout:

•

Please put the CVCAP, CVCCand RIREF as close to the device as possible. Also, TI recommends to put the

ground plane as Figure 59 and Figure 60.

•

Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat

flow path from the package to the ambient is through copper on the PCB. Maximum copper density is

extremely important when no heat sinks are attached to the PCB on the other side from the package.

•

Add as many thermal vias as possible directly under the package ground pad to optimize the thermal

conductivity of the board.

•

Use either plated-shut or plugged and capped vias for all the thermal vias on both sides of the board to

prevent solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.

LP5018 Datasheet(PDF) 41 Page - Texas Instruments