ENS210 datasheet(14/43 Pages) AMSCO

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[v1-02] 2018-Feb-19

ENS210 − Functional Description

This register address is stored in an internal CRA register

(“Current Register Address”). Finally, the master sends the 8 bit

when the address is not writeable). This value is written to the

1. Optionally, the master sends more 8 bit values, for the next

registers (auto incrementing CRA), each of which is (n)ack’ed by

the slave. Finally, the master generates a stop condition “p”,

unblocking the bus for other transactions.

A read transaction (see Figure 16 b) starts with a write (of the

following format. The master initiates the transaction with a

start condition. Next, the master sends the 7 bits ENS210 slave

address followed by a 1 bit direction (a 0 indicating write). This

byte is acknowledged by the slave. The master continues by

sending the 8 bit register address, which is acknowledged by the

slave and stored in the CRA register. Then the master sends

another start condition (a so-called repeated start condition,

keeping the bus blocked) followed by the 7 bits ENS210 slave

address followed by a 1 bit direction (a 1 indicating read “r”),

which is acknowledged by the slave. Next, the slave sends an 8

bits register value from the register pointed to by the CRA

acknowledged by the master. The master may read another 8

bits (auto increment feature) from the slave and acknowledge

that, until the master sends a nack “n” followed by a stop to

unblock the bus.

The ENS210 has an 8 bit address space, potentially addressing

256 registers. In reality, only few addresses are actually backed

by a register (see Register Overview). All other addresses are

reserved. A write transaction to a reserved (or read-only) register

causes a not-acknowledge. A read transaction for a reserved

ENS210 Datasheet(PDF) 14 Page - ams AG