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Semiconductor

ML670100

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PIN DESCRIPTIONS

Type

Signal

Name

I/O Direction Description

Address

bus

XA23 -

XA16

Output

These are bits 23-16 of the external address bus. They represent

secondary functions for I/O port PIO0[7:0].

XA15 -

XA0

Output

These are bits 15 - 0 of the external address bus.

Data bus XD15 -

XD8

Bidirectional These are bits 15-8 of the external data bus. They represent

secondary functions for I/O port PIO1[7:0].

XD7- -XD0 Bidirectional These are bits 7-0 of the external data bus.

Bus

nCS0

Output

This output is the chip select signal for bank 0.

control

signals

nCS1

Output

This output is the chip select signal for bank 1. It represents a

secondary function for I/O port PIO2[6].

nRD

Output

This output is the read signal for SRAM banks (0 and 1).

nWRL

Output

This output is the Write Enable Low signal for SRAM banks (0

and 1).

nWRH

Output

This output is the Write Enable High signal for SRAM banks (0

and 1).

It represents a secondary function for I/O port

PIO2[5].

nWRE

Output

This output is the Write Enable signal for SRAM banks (0 and

1).

nLB

Output

This output is the Low Byte Select signal for SRAM banks (0

and 1).

nHB

Output

This output is the High Byte Select signal for SRAM banks (0

and 1). It represents a secondary function for I/O port PIO2[5].

nRAS0

Output

This output is the Row Address Strobe signal for bank 2.

It represents a secondary function for I/O port PIO2[2].

nRAS1

Output

This output is the Row Address Strobe signal for banks 3.

It represents a secondary function for I/O port PIO2[4].

nCASL

Output

This output is the Column Address Strobe Low signal for

DRAM banks (2 and 3). It represents a secondary function for

I/O port PIO2[1].

nCASH

Output

This output is the Column Address Strobe High signal for

DRAM banks (2 and 3). It represents a secondary function for

I/O port PIO2[3].

nWE

Output

This output is the Write Enable signal for DRAM banks (2 and

3). It represents a secondary function for I/O port PIO2[0].

nCAS

Output

This output is the Column Address Strobe signal for DRAM

banks (2 and 3). It represents a secondary function for I/O port

PIO2[1].

nWH

Output

This output is the Write Enable High signal for DRAM banks

(2 and 3). It represents a secondary function for I/O port

PIO2[3].

nWL

Output

This output is the Write Enable Low signal for DRAM banks (2

and 3). It represents a secondary function for I/O port PIO2[0].

nXWAIT

Input

This input pin controls insertion of wait cycles. It represents a

secondary function for I/O port PIO2[7].

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