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EM6580 Datasheet(PDF) 36 Page - EM Microelectronic - MARIN SA |
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EM6580 Datasheet(HTML) 36 Page - EM Microelectronic - MARIN SA |
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36 / 55 page  R EM6580 Copyright © 2007, EM Microelectronic-Marin SA 03/07, rev. J 36 www.emmicroelectronic.com 10. ADC/SVLD Comparator characteristics band-gag (360mV) tested level - comparator hyst. Level Comparator output Comparator hysteresis is adaptive in 4 steps controlled by MSB of RegSVLDlev register to cover all tested levels from 0.5V to 3.0V to give a typ. “tested level” hysteresis of 40mV. Negative hysteresis on comparator is implemented to eliminate comparator output oscillation arround switching point. 11. RAM The EM6580 has one 80x4 bit static RAM built-in located on addresses hex 0 to 4F. All the RAM nibbles are direct addressable. Figure 24. RAM Architecture RAM 80 x 4 = direct addressable Adr [hex] RAM location Read / Write 4F RAM_79 4 bit R/W 4E RAM_78 4 bit R/W 4D RAM_77 4 bit R/W 4B RAM_76 4 bit R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 04 RAM_04 4 bit R/W 03 RAM_03 4 bit R/W 02 RAM_02 4 bit R/W 01 RAM_01 4 bit R/W 00 RAM_00 4 bit R/W RAM Extension : Unused R/W Registers can often be used as possible RAM extension. Be careful not to use registers which start, stop, or reset some functions. |
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