EM6580 datasheet(28/55 Pages) EMMICRO

28 / 55 page

EM6580

03/07, rev. J

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8.3 Event Counting

The counter can be used in a special event count mode where a certain number of events (clocks) on the PA[1]

(only non-debounced and only rising edge) or PA[3/4] input are counted. In this mode the counting will start

directly on the next active clock edge on the selected port A input.

Figure 18. Internal Clock Synchronization

The Event Count mode is switched on by setting bit EvCount in the register RegCCntl2 to ‘1’. PA[3] or PA[4]

input depending on IrqPA[3l/4h] bit in RegPaCntl1 can be inverted depending on edgeFallingPA[3/4] in

in the same register. Its frequency depends on the bit DebSel from register RegPresc setting. Refer also to

Figure 10 for PortA Inputs Function. As already said for other PA[1] input only possibility is to count rising non-

debounced edges.

A previously loaded register value (CReg[9:0]) can be compared against the actual counter value

(Count[9:0]). If the two are matching (equality) then an interrupt (IRQComp) is generated. The compare

function is switched on with the bit EnComp in the register RegCCntl2. With EnComp = 0 no IRQComp is

generated. Starting the counter with the same value as the compare register is possible, no IRQ is generated

on start. Full or Limited bit compare are possible, defined by bit SelIntFull in register RegSysCntl1.

EnComp must be written after a load operation (Load = 1). Every load operation resets the bit EnComp.

Full bit compare function.

Bit SelIntFull is set to ‘1’. The function behaves as described above independent of the selected counter

length. Limited bit counting together with full bit compare can be used to generate a certain amount of

IRQCount0 interrupts until the counter generates the IRQComp interrupt. With PWMOn=‘1’ the counter would

have automatically stopped after the IRQComp, with PWMOn=‘0’ it will continue until the software stops it.

EnComp must be cleared before setting SelIntFull and before starting the counter again. Be careful,

PWMoutPA[0] also redefines the port PA[0] or PWMoutPA[1] the PA[1] output data. (refer to section 8.4).

The signal PWMOn is acombination of PWMOutPA[0], PWMOutPA[1], SerialCkPA[1]

PWMOn = (PWMOutPA[0] OR PWMOutPA[1]) AND NOT(SeriaCktPA[1]))

Limited bit compare

With the bit SelIntFull set to ‘0’ (default) the compare function will only take as many bits into account as

defined by the counter length selection BitSel[1:0] (see chapter 6.3).

8.4 Pulse Width Modulation (PWM)

The PWM generator uses the behavior of the Compare function (see above) so EnComp must be set to

activate the PWM function.. At each Roll Over or Compare Match the PWM state - which is output on port

PA[0] or PA[1] - will toggle. The start value on PA[0] or PA[1] is forced while EnComp is 0 the value is

depending on the up or down count mode. Every counter value load operation resets the bit EnComp and

therefore the PWM start value is reinstalled.

One can output PWM signal to PA[0] or PA[1]. Setting PWMoutPA[0] to ‘1’ in register RegPaCntl3 routes the

counter PWM output to PA[0]. Insure that PA[0] is set to output mode. Setting PWMoutPA[1] to ‘1’ in register

RegPaCntl3 routes the counter PWM output to PA[1]. Insure that PA[1] is set to output mode. Refer to section

6.3 and 6.4 for the port A output setup.

Start

Count[9:0

]

+ / - 1

EvCount = 0

Start

EvCount = 0

Start

EvCount = 1

Start

EvCount = 1

Count[9:0

]

+ / - 1

Count[9:0

]

Count[9:0

]

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