EM6580WS11 datasheet(13/55 Pages) EMMICRO

13 / 55 page

EM6580

03/07, rev. J

www.emmicroelectronic.com

Table 5.3.2 Control of Prescaler Register RegPresc

Bit

Name

Reset

R/W

Description

ExtCPUclkON

R/W

Ext. Clock selection instead of RC oscillator for CPUClk.

ResPresc

R/W

Write Reset prescaler

Reset the divider chain from Ck[14] to Ck[2], sets Ck[1].

No action.

The Read value is always '0'

PrIntSel

R/W

Prescaler Interrupt select. 0

Interrupt from Ck[4] (typ. 8/12 Hz)

Interrupt from Ck[7] (typ. 64/97 Hz)

DebSel

R/W

Debouncer clock select. 0

Debouncer with Ck[8]

Debouncer with Ck[11] or Ck[14]

p* reset to ‘0’ by POR only.

With DebSel = 1 one may choose either the Ck[11] or Ck[14] debouncer frequency by selecting the

corresponding register mask option.(Refer to RegMFP1 table chapter 14.8) Relative to 32kHz the

corresponding max. debouncer times are then 2 ms or 0.25 ms. For the register option selection refer to

chapter 14.8

Switching the PrIntSel may generate an interrupt request. Avoid it with MaskIRQ64/8 = 0 selection during the

switching operation.

The prescaler contains 2 interrupt sources:

- IRQ64/8 ; this is Ck[7] or Ck[4] positive edge interrupt, the selection is depending on bit PrIntSel.

- IRQHz1 ; this is Ck[1] positive edge interrupt

There is no interrupt generation on reset.

The first IRQHz1 Interrupt occurs typically. 1 sec (if SysClk = 32kHz) after reset. (0.65 sec if SysClk is 50kHz).

NOTE: If not written explicitly all timing in peripherals is calculated for 32 kHz System Clock !

EM6580WS11 Datasheet(PDF) 13 Page - EM Microelectronic - MARIN SA