EM6580WS11 datasheet(2/55 Pages) EMMICRO

2 / 55 page

EM6580

03/07, rev. J

www.emmicroelectronic.com

EM6580 at a glance

Power Supply

- Low voltage low power architecture

including internal voltage regulator

- 2.3V to 5.5V supply voltage

- 5.8 µA in active mode

- 3.3 µA in standby mode

- 0.32 µA in sleep mode

RAM

- 80 x 4 bit, directly addressable

FLASH

- 4096 x 16 bit (8k Byte),

CPU

- 4-bit RISC architecture

- 2 clock cycles per instruction (CPI=2)

- 72 basic instructions

Main Operating Modes and Resets

- Active mode (CPU is running)

- Standby mode (CPU in halt, peripherals running)

- Sleep mode (no clock, data kept)

- Initial Power-On-Reset with Power-Check

- Watchdog reset (logic)

- Reset terminal (software option on PA[3/4])

- Sleep Counter reset from Sleep mode

- Wakeup on change from Sleep mode

Prescaler

- Divider (4 stages) to best fit CPU clock (32kHz – 1MHz

to 32kHz system clock to keep peripherals timing close

to specification

- 15 stage system clock divider from 32kHz down to 1Hz

- 2 Interrupt requests (3 different frequencies)

- Prescaler reset (4kHz to 1Hz)

8-Bit Serial Interface

- 3 wire (Clock, DataIn , DataOut) master/slave mode

- READY output during data transfer

- Maximum shift clock is equal to the main system clock

- Interrupt request to the CPU after 8 bit data transfer

- Supports different serial formats

- pins shared with general 4 bit PA[3:0] I/O port

Oscillator

- RC Oscillator range: 32kHz up to 800kHz

- No external components are necessary

- Temperature compensated

- External clock source possible from PA[1]

4(5)-Bit I/O PA[3:0] & PA[4] / PA[5]*

- Direct input read on the port terminals

- 2 debounced function available muxed on 4 inputs

- 2 Interrupt request on positive or negative edge

- Pull-up or pull-down or none selectable by register

- 2 Test variables (software) for conditional jumps

- PA[1] and PA[3/4] are inputs for the event counter

- PA[3/4] Reset input (register selectable)

- All outputs can be put tri-state (default)

- Selectable pull-downs in input mode

- CMOS or Nch. open drain outputs

- Weak pull-up selectable in Nch. open drain

mode

4-bit ADC & Voltage Level Det. (SVLD)

- External voltage compare from PA[4] input possible (low

resolution 4 bit AD converter)

-7 different levels from 2 V to 3.0 V for SVLD

- Used for Power Check after POR (2.0V check)

- Busy flag during measure

- Interrupt generated if SVLD measurement low

10-Bit Universal Counter

- 10, 8, 6 or 4 bit up/down counting

- Parallel load

- Event counting (PA[1] or PA[3/4])

- 8 different input clocks

- Full 10 bit or limited (8, 6, 4 bit) compare function

- 2 interrupt requests (on compare and on 0)

- Hi-frequency input on PA[1] and PA[3/4] or CPUClk

- Pulse width modulation (PWM) output

Interrupt Controller

- 2 external and 6 internal interrupt request sources

- Each interrupt request can individually be masked

- Each interrupt flag can individually be reset

- Automatic reset of each interrupt request after read

- General interrupt request to CPU can be disabled

- Automatic enabling of general interrupt request flag

when going into HALT mode

Sleep Counter Reset (SCR)

- wake up the EM6580 from sleep mode

- 4 timings selectable by register

- Inhibit SCR by register

Package form available

- SO-8/14

- Die form (9 pin possible due to additional I/O pin)

NB: All frequencies written in this document are related to a typical system clock of 32 kHz !

EM6580WS11 Datasheet(PDF) 2 Page - EM Microelectronic - MARIN SA

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