PC7410 datasheet(21/54 Pages) ATMEL

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PC7410

2141D–HIREL–02/04

Figure 8. SYSCLK Input Timing Diagram

Note:

VM = Midpoint Voltage (OV

DD/2)

Processor Bus AC

Specifications

Table 11 provides the processor AC timing specifications for the PC7410 as defined in

Figure 10 and Figure 11. Timing specifications for the L2 bus are provided in “L2 Bus

AC Specifications” on page 26.

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input

SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-

nal in question. All output timings assume a purely resistive 50

Ω load (see Figure 10). Input and output timings are

measured at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of

(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals

(I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV

symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can

be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of

the reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output

went invalid (OX).

3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 11).

4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of

255 bus clocks after the PLL re-lock time during the power-on reset sequence.

5. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds(ns). The numbers given in the table must be multiplied

by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.

6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3]

SYSCLK

CVIL

CVIH

tKHKL

tSYSCLK

tKR

tKF

Table 11. Processor Bus AC Timing Specifications(1) at V

DD = AVDD = 1.8V ± 100 mV;

-55°C

≤ T

j ≤ 125°C, OVDD = 1.8V ± 100 mV

Symbol(2)

Parameter

400, 450, 500 MHz

Unit

Min

Max

tIVKH

Input Setup

1.0

–

IXKH

Input Hold

0–

KHTSV

tKHARV

tKHOV

Output Valid Times:(7)(8)

ARTRY/SHD0/SHD1

All Other Outputs

–

3.0

2.3

3.0

tKHTSX

KHARX

KHOX

Output Hold Times:(7)(12)

ARTRY/SHD0/SHD1

All Other Outputs

0.5

–

KHOE

(11)

SYSCLK to Output Enable

0.5

–

tKHOZ

SYSCLK to Output High Impedance (all except ABB/AMON[0], ARTRY/SHD,

DBB/DMON[0]), SHD0, SHD1)

–3.5

KHABPZ

(5)(9)(11)

SYSCLK to ABB/AMON[0], DBB/DMON[0] High Impedance after precharge

–

SYSCLK

tKHARP

(5)(10)(11)

Maximum Delay to ARTRY/SHD0/SHD1 Precharge

–

SYSCLK

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