LAN91C110 datasheet(3/55 Pages) SMSC

3 / 55 page

FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications

SMSC DS – LAN91C110 REV. B

Page 3

Rev. 09/05/02

TABLE OF CONTENTS

FEATURES................................................................................................................................1

GENERAL DESCRIPTION ........................................................................................................1

FUNCTIONAL DESCRIPTION ..................................................................................................9

DATA STRUCTURES AND REGISTERS...............................................................................13

TYPICAL FLOW OF EVENTS FOR TRANSMIT (AUTO RELEASE = 0) ..................................................36

TYPICAL FLOW OF EVENTS FOR TRANSMIT (AUTO RELEASE = 1) ..................................................37

TYPICAL FLOW OF EVENTS FOR RECEIVE.....................................................................................38

OPERATIONAL DESCRIPTION .............................................................................................46

MAXIMUM GUARANTEED RATINGS* ...................................................................................46

DC ELECTRICAL CHARACTERISTICS..................................................................................46

TIMING DIAGRAMS ................................................................................................................49

LAN91C110 REV. B REVISIONS ..........................................................................................55

LIST OF TABLES

TABLE 1 - DESCRIPTION OF PIN FUNCTIONS........................................................................................................5

TABLE 2 - BUFFER TYPES ..........................................................................................................................................7

TABLE 3 - INTERNAL I/O SPACE MAPPING.....................................................................................................................16

TABLE 4 - PIN PACKAGE OUTLINE TABLE....................................................................................................................54

LIST OF FIGURES

FIGURE 1 - PIN CONFIGURATION .............................................................................................................................4

FIGURE 2 - LAN91C110 BLOCK DIAGRAM ..............................................................................................................8

FIGURE 3 - LAN91C110 SYSTEM DIAGRAM............................................................................................................8

FIGURE 4 - LAN91C110 INTERNAL BLOCK DIAGRAM WITH DATAPATH......................................................12

FIGURE 5 - DATA PACKET FORMAT ......................................................................................................................13

FIGURE 6 - INTERRUPT STRUCTURE .....................................................................................................................31

FIGURE 7 - INTERRUPT SERVICE ROUTINE .........................................................................................................39

FIGURE 8- RX INTR ....................................................................................................................................................40

FIGURE 9 - TX INTR....................................................................................................................................................41

FIGURE 10 - TXEMPTY INTR (ASSUMES AUTO RELEASE OPTION SELECTED)............................................................42

FIGURE 11 - DRIVE SEND AND ALLOCATE ROUTINES......................................................................................43

FIGURE 12 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU ....................................................45

FIGURE 13 - ASYNCHRONOUS CYCLE - NADS=0.................................................................................................49

FIGURE 14 - ASYNCHRONOUS CYCLE - USING NADS ........................................................................................49

FIGURE 15 - ADDRESS LATCHING FOR ALL MODES..........................................................................................50

FIGURE 16 - SRAM INTERFACE ...............................................................................................................................51

FIGURE 17 - MII INTERFACE ........................................................................................................................................53

FIGURE 18 - 144 PIN TQFP PACKAGE OUTLINES.........................................................................................................54

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